A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique

Yen Long Lee, Soon Jyh Chang

研究成果: Conference contribution

摘要

This paper presents a 6 Gb/s low-power half-rate equalizer. Compared with the current steering summation circuits, the proposed charge-average switched-capacitor equalizer achieves good energy and area efficiency, and thus is suitable for multi-lane applications. The proposed architecture are majorly constructed by switched-capacitor and digital circuitries, it is hence suitable for advanced manufacturing process. The proof-of-concept prototype was fabricated in TSMC 0.18 um CMOS technology. It occupies 0.0034 mm2 area and the figure of merit is 10 fJ/bit/dB while operating at a bit-error-rate < 10-12 for 6 Gb/s data passed over a 100 cm FR4 PCB channel with 23.2 dB channel loss at 3 GHz.

原文English
主出版物標題2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509024391
DOIs
出版狀態Published - 2016 八月 12
事件5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan
持續時間: 2016 五月 42016 五月 6

出版系列

名字2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Other

Other5th International Symposium on Next-Generation Electronics, ISNE 2016
國家Taiwan
城市Hsinchu
期間16-05-0416-05-06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

指紋 深入研究「A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique」主題。共同形成了獨特的指紋。

引用此