A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique

Yen Long Lee; Soon Jyh Chang

doi:10.1109/ISNE.2016.7543355

A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique

Yen Long Lee, Soon Jyh Chang

電機工程學系

研究成果: Conference contribution

摘要

This paper presents a 6 Gb/s low-power half-rate equalizer. Compared with the current steering summation circuits, the proposed charge-average switched-capacitor equalizer achieves good energy and area efficiency, and thus is suitable for multi-lane applications. The proposed architecture are majorly constructed by switched-capacitor and digital circuitries, it is hence suitable for advanced manufacturing process. The proof-of-concept prototype was fabricated in TSMC 0.18 um CMOS technology. It occupies 0.0034 mm² area and the figure of merit is 10 fJ/bit/dB while operating at a bit-error-rate < 10^-12 for 6 Gb/s data passed over a 100 cm FR4 PCB channel with 23.2 dB channel loss at 3 GHz.

原文	English
主出版物標題	2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781509024391
DOIs	https://doi.org/10.1109/ISNE.2016.7543355
出版狀態	Published - 2016 八月 12
事件	5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan 持續時間: 2016 五月 4 → 2016 五月 6

出版系列

名字	2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Other

Other	5th International Symposium on Next-Generation Electronics, ISNE 2016
國家	Taiwan
城市	Hsinchu
期間	16-05-04 → 16-05-06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

存取文件

10.1109/ISNE.2016.7543355

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引用此

Lee, Y. L., & Chang, S. J. (2016). A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique. 於 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016 [7543355] (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISNE.2016.7543355

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abstract = "This paper presents a 6 Gb/s low-power half-rate equalizer. Compared with the current steering summation circuits, the proposed charge-average switched-capacitor equalizer achieves good energy and area efficiency, and thus is suitable for multi-lane applications. The proposed architecture are majorly constructed by switched-capacitor and digital circuitries, it is hence suitable for advanced manufacturing process. The proof-of-concept prototype was fabricated in TSMC 0.18 um CMOS technology. It occupies 0.0034 mm2 area and the figure of merit is 10 fJ/bit/dB while operating at a bit-error-rate < 10-12 for 6 Gb/s data passed over a 100 cm FR4 PCB channel with 23.2 dB channel loss at 3 GHz.",

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Lee, YL & Chang, SJ 2016, A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique. 於 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016., 7543355, 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016, Institute of Electrical and Electronics Engineers Inc., 5th International Symposium on Next-Generation Electronics, ISNE 2016, Hsinchu, Taiwan, 16-05-04. https://doi.org/10.1109/ISNE.2016.7543355

A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique. / Lee, Yen Long; Chang, Soon Jyh.

2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7543355 (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016).

研究成果: Conference contribution

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N2 - This paper presents a 6 Gb/s low-power half-rate equalizer. Compared with the current steering summation circuits, the proposed charge-average switched-capacitor equalizer achieves good energy and area efficiency, and thus is suitable for multi-lane applications. The proposed architecture are majorly constructed by switched-capacitor and digital circuitries, it is hence suitable for advanced manufacturing process. The proof-of-concept prototype was fabricated in TSMC 0.18 um CMOS technology. It occupies 0.0034 mm2 area and the figure of merit is 10 fJ/bit/dB while operating at a bit-error-rate < 10-12 for 6 Gb/s data passed over a 100 cm FR4 PCB channel with 23.2 dB channel loss at 3 GHz.

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Lee YL, Chang SJ. A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique. 於 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7543355. (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016). https://doi.org/10.1109/ISNE.2016.7543355