TY - GEN
T1 - A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique
AU - Lee, Yen Long
AU - Chang, Soon Jyh
PY - 2016/8/12
Y1 - 2016/8/12
N2 - This paper presents a 6 Gb/s low-power half-rate equalizer. Compared with the current steering summation circuits, the proposed charge-average switched-capacitor equalizer achieves good energy and area efficiency, and thus is suitable for multi-lane applications. The proposed architecture are majorly constructed by switched-capacitor and digital circuitries, it is hence suitable for advanced manufacturing process. The proof-of-concept prototype was fabricated in TSMC 0.18 um CMOS technology. It occupies 0.0034 mm2 area and the figure of merit is 10 fJ/bit/dB while operating at a bit-error-rate < 10-12 for 6 Gb/s data passed over a 100 cm FR4 PCB channel with 23.2 dB channel loss at 3 GHz.
AB - This paper presents a 6 Gb/s low-power half-rate equalizer. Compared with the current steering summation circuits, the proposed charge-average switched-capacitor equalizer achieves good energy and area efficiency, and thus is suitable for multi-lane applications. The proposed architecture are majorly constructed by switched-capacitor and digital circuitries, it is hence suitable for advanced manufacturing process. The proof-of-concept prototype was fabricated in TSMC 0.18 um CMOS technology. It occupies 0.0034 mm2 area and the figure of merit is 10 fJ/bit/dB while operating at a bit-error-rate < 10-12 for 6 Gb/s data passed over a 100 cm FR4 PCB channel with 23.2 dB channel loss at 3 GHz.
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U2 - 10.1109/ISNE.2016.7543355
DO - 10.1109/ISNE.2016.7543355
M3 - Conference contribution
AN - SCOPUS:84985993122
T3 - 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
BT - 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th International Symposium on Next-Generation Electronics, ISNE 2016
Y2 - 4 May 2016 through 6 May 2016
ER -