A 10 nm MOSFET concept

J. Appenzeller, R. Martel, P. Solomon, K. Chan, Ph Avouris, J. Knoch, J. Benedict, M. Tanner, S. Thomas, K. L. Wang, J. A. Del Alamo

研究成果: Article同行評審

18 引文 斯高帕斯(Scopus)


In the present work we describe a concept for the fabrication of a 10 nm MOSFET. The combination of an epitaxial silicon structure based on SOI with an anisotropic etch allows the definition of ultra-short channel devices. By cutting through a highly doped n++ layer on top of an undoped channel layer using a KOH-etch, source and drain as well as the channel itself are defined in one step. Since the etch produces a V-like groove, an extremely small source/drain separation - defined by the tip region of the V - can be obtained. We claim that even standard optical lithography can be used in principle to generate channels of around 10 nm length. Measured output characteristics on first prototypes indicate the possibility of using the proposed concept to generate functioning MOSFETs with acceptable short-channel effects.

頁(從 - 到)213-219
期刊Microelectronic Engineering
出版狀態Published - 2001 5月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 原子與分子物理與光學
  • 凝聚態物理學
  • 表面、塗料和薄膜
  • 電氣與電子工程


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