A 100-Channel 1-mW implantable neural recording IC

Xiaodan Zou, Lei Liu, Jia Hao Cheong, Lei Yao, Peng Li, Ming Yuan Cheng, Wang Ling Goh, Ramamoorthy Rajkumar, Gavin Stewart Dawe, Kuang Wei Cheng, Minkyu Je

研究成果: Article同行評審

92 引文 斯高帕斯(Scopus)

摘要

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μV \rm rms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μhbox m standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.

原文English
文章編號6479332
頁(從 - 到)2584-2596
頁數13
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
60
發行號10
DOIs
出版狀態Published - 2013

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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