A 100 W 5.1-channel digital class-D audio amplifier with single-chip design

Jia Ming Liu, Shih Hsiung Chien, Tai Haur Kuo

研究成果: Article

22 引文 斯高帕斯(Scopus)

摘要

A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma modulators (DSMs), and pulse-width modulation (PWM) generators, is implemented with a standard CMOS digital cell-library. A dual-loop resonator is proposed to increase the stable input range of the DSM so that the low-distortion output power of the class-D amplifier can be increased. For the HV portion, distortion caused by parasitic resistances of the power stage is analyzed to obtain a better design. A multi-phase PWM switching technique is proposed to prevent the multi-channel output stages from simultaneously switching, and thus the supply bouncing can be reduced. An over-current protection circuit with high supply noise immunity is also presented. Fabricated with 0.35/3-μm 3.3/18-V 1P3M CMOS technology, the 5.1-channel amplifier achieves a total root-mean-square (RMS) output power of 100 W, a distortion of less than 0.7%, and a power efficiency of 88% with a total chip area of 48.9 mm 2.

原文English
文章編號6177693
頁(從 - 到)1344-1354
頁數11
期刊IEEE Journal of Solid-State Circuits
47
發行號6
DOIs
出版狀態Published - 2012 四月 5

    指紋

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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