TY - JOUR
T1 - A 100 W 5.1-channel digital class-D audio amplifier with single-chip design
AU - Liu, Jia Ming
AU - Chien, Shih Hsiung
AU - Kuo, Tai Haur
N1 - Funding Information:
Manuscript received September 22, 2011; revised January 30, 2012; accepted January 31, 2012. Date of publication April 03, 2012; date of current version May 22, 2012. This paper was approved by Associate Editor Jan Craninckx. This work was supported by Advanic Tech. Inc, Tainan, Taiwan, and Cheertek Tech. Inc., Hsinchu, Taiwan. This work was also supported in part by the National Science Council of Taiwan, under Grant NSC 99-2221-E-006-218-MY3.
PY - 2012
Y1 - 2012
N2 - A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma modulators (DSMs), and pulse-width modulation (PWM) generators, is implemented with a standard CMOS digital cell-library. A dual-loop resonator is proposed to increase the stable input range of the DSM so that the low-distortion output power of the class-D amplifier can be increased. For the HV portion, distortion caused by parasitic resistances of the power stage is analyzed to obtain a better design. A multi-phase PWM switching technique is proposed to prevent the multi-channel output stages from simultaneously switching, and thus the supply bouncing can be reduced. An over-current protection circuit with high supply noise immunity is also presented. Fabricated with 0.35/3-μm 3.3/18-V 1P3M CMOS technology, the 5.1-channel amplifier achieves a total root-mean-square (RMS) output power of 100 W, a distortion of less than 0.7%, and a power efficiency of 88% with a total chip area of 48.9 mm 2.
AB - A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma modulators (DSMs), and pulse-width modulation (PWM) generators, is implemented with a standard CMOS digital cell-library. A dual-loop resonator is proposed to increase the stable input range of the DSM so that the low-distortion output power of the class-D amplifier can be increased. For the HV portion, distortion caused by parasitic resistances of the power stage is analyzed to obtain a better design. A multi-phase PWM switching technique is proposed to prevent the multi-channel output stages from simultaneously switching, and thus the supply bouncing can be reduced. An over-current protection circuit with high supply noise immunity is also presented. Fabricated with 0.35/3-μm 3.3/18-V 1P3M CMOS technology, the 5.1-channel amplifier achieves a total root-mean-square (RMS) output power of 100 W, a distortion of less than 0.7%, and a power efficiency of 88% with a total chip area of 48.9 mm 2.
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U2 - 10.1109/JSSC.2012.2188465
DO - 10.1109/JSSC.2012.2188465
M3 - Article
AN - SCOPUS:84861719095
SN - 0018-9200
VL - 47
SP - 1344
EP - 1354
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 6
M1 - 6177693
ER -