A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chun Cheng Liu, Soon Jyh Chang, Guan Ying Huang, Ying Zu Lin, Chung Ming Huang, Chih Hao Huang, Linkai Bu, Chih Chung Tsai

研究成果: Conference contribution

224 引文 斯高帕斯(Scopus)

摘要

In recent years, due to the improvements in CMOS technologies, medium resolution (8 to 10b) SAR ADCs have been able to achieve sampling rates of several tens of MS/s with excellent power efficiency and small area [1]-[4]. When the sampling rate increases, the SAR ADCs suffer from settling issues. In a typical 10b 100MS/s ADC, when the sampling settling time, comparator active time and SAR logic delay are subtracted from each period, the DAC settling time has to be less than 0.4ns in each bit cycle. Such a short time interval is not sufficient for the capacitive DAC to stabilize because the increasing interconnect line impedance in advanced processes slows down the charge transfer, especially in the longest routing path of the DAC capacitor network. Furthermore, the reference voltage sinks noise and line coupling also affects the settling. A non-binary SAR can tolerate DAC settling error at the cost of increased design complexity and hardware overhead [1]. This paper reports a 10b SAR ADC that uses binary-scaled DAC networks for settling error compensation. The ADC achieves 100MS/s while consuming only 1.13mW.

原文English
主出版物標題2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
頁面386-387
頁數2
DOIs
出版狀態Published - 2010 五月 18
事件2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States
持續時間: 2010 二月 72010 二月 11

出版系列

名字Digest of Technical Papers - IEEE International Solid-State Circuits Conference
53
ISSN(列印)0193-6530

Other

Other2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
國家United States
城市San Francisco, CA
期間10-02-0710-02-11

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

指紋 深入研究「A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation」主題。共同形成了獨特的指紋。

  • 引用此

    Liu, C. C., Chang, S. J., Huang, G. Y., Lin, Y. Z., Huang, C. M., Huang, C. H., Bu, L., & Tsai, C. C. (2010). A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. 於 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (頁 386-387). [5433970] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 卷 53). https://doi.org/10.1109/ISSCC.2010.5433970