A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS

Guan Ying Huang, Soon Jyh Chang, Ying Zu Lin, Chun Cheng Liu, Chun Po Huang

研究成果: Conference contribution

31 引文 斯高帕斯(Scopus)

摘要

This paper reports a successive-approximation analog-to-digital converter (ADC) which combines the bypass window and direct switching technique to tolerate the incomplete settling error and reduce the control logic delay. A small unit capacitor cell reduces the power consumption and settling time. The 10-bit prototype is fabricated in a 40nm CMOS process. At 200 MS/s and 0.9-V supply, this ADC consumes 0.82 mW and achieves an SNDR of 57.16 dB, resulting in an FOM of 13.9 fJ/Conversion-step.

原文English
主出版物標題Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
頁面289-292
頁數4
DOIs
出版狀態Published - 2013 十二月 1
事件2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore
持續時間: 2013 十一月 112013 十一月 13

出版系列

名字Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Other

Other2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
國家Singapore
城市Singapore
期間13-11-1113-11-13

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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