TY - GEN
T1 - A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS
AU - Huang, Guan Ying
AU - Chang, Soon Jyh
AU - Lin, Ying Zu
AU - Liu, Chun Cheng
AU - Huang, Chun Po
PY - 2013/12/1
Y1 - 2013/12/1
N2 - This paper reports a successive-approximation analog-to-digital converter (ADC) which combines the bypass window and direct switching technique to tolerate the incomplete settling error and reduce the control logic delay. A small unit capacitor cell reduces the power consumption and settling time. The 10-bit prototype is fabricated in a 40nm CMOS process. At 200 MS/s and 0.9-V supply, this ADC consumes 0.82 mW and achieves an SNDR of 57.16 dB, resulting in an FOM of 13.9 fJ/Conversion-step.
AB - This paper reports a successive-approximation analog-to-digital converter (ADC) which combines the bypass window and direct switching technique to tolerate the incomplete settling error and reduce the control logic delay. A small unit capacitor cell reduces the power consumption and settling time. The 10-bit prototype is fabricated in a 40nm CMOS process. At 200 MS/s and 0.9-V supply, this ADC consumes 0.82 mW and achieves an SNDR of 57.16 dB, resulting in an FOM of 13.9 fJ/Conversion-step.
UR - http://www.scopus.com/inward/record.url?scp=84893558119&partnerID=8YFLogxK
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U2 - 10.1109/ASSCC.2013.6691039
DO - 10.1109/ASSCC.2013.6691039
M3 - Conference contribution
AN - SCOPUS:84893558119
SN - 9781479902781
T3 - Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
SP - 289
EP - 292
BT - Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
T2 - 2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Y2 - 11 November 2013 through 13 November 2013
ER -