This paper presents an 11-bit 35-MS/s wide input range successive approximation register (SAR) analog-to-digital converter (ADC). A built-in magnitude-reduction front-end circuit is integrated with the SAR ADC to deal with high voltage input signal without using power-hungry programmable gain amplifier (PGA). The front-end circuit is implemented by switched-capacitor (SC) circuit without high voltage devices, which is low power, compact and easy to integrate with the SAR ADC. The proof-of-concept prototype was fabricated in TSMC 180-nm CMOS technology. At 1.8V supply and Nyquist input frequency, the ADC achieves an SNDR of 67.89 dB and total power consumption of 3.4 mW (including front-end circuit), resulting in a figure-of-merit (FoM) of 47.96 fJ/conv.-step.