A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process

Wen Chia Luo, Soon Jyh Chang, Chun Po Huang, Hao Sheng Wu

研究成果: Conference contribution

摘要

This paper presents an 11-bit 35-MS/s wide input range successive approximation register (SAR) analog-to-digital converter (ADC). A built-in magnitude-reduction front-end circuit is integrated with the SAR ADC to deal with high voltage input signal without using power-hungry programmable gain amplifier (PGA). The front-end circuit is implemented by switched-capacitor (SC) circuit without high voltage devices, which is low power, compact and easy to integrate with the SAR ADC. The proof-of-concept prototype was fabricated in TSMC 180-nm CMOS technology. At 1.8V supply and Nyquist input frequency, the ADC achieves an SNDR of 67.89 dB and total power consumption of 3.4 mW (including front-end circuit), resulting in a figure-of-merit (FoM) of 47.96 fJ/conv.-step.

原文English
主出版物標題2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1-4
頁數4
ISBN(電子)9781538642603
DOIs
出版狀態Published - 2018 六月 5
事件2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan
持續時間: 2018 四月 162018 四月 19

出版系列

名字2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Other

Other2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
國家Taiwan
城市Hsinchu
期間18-04-1618-04-19

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality
  • Control and Optimization
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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