摘要
This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.
| 原文 | English |
|---|---|
| 頁（從 - 到） | 881-890 |
| 頁數 | 10 |
| 期刊 | IEEE Transactions on Circuits and Systems I: Regular Papers |
| 卷 | 65 |
| 發行號 | 3 |
| DOIs | |
| 出版狀態 | Published - 2018 三月 |
指紋
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
引用此文
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A 12-b 40-MS/s Calibration-Free SAR ADC. / Hsu, Chung Wei; Chang, Soon Jyh; Huang, Chun Po; Chang, Li Jen; Shyu, Ya Ting; Hou, Chih Huei; Tseng, Hwa An; Kung, Chih Yuan; Hu, Huan Jui.
於: IEEE Transactions on Circuits and Systems I: Regular Papers, 卷 65, 編號 3, 03.2018, p. 881-890.研究成果: Article
TY - JOUR
T1 - A 12-b 40-MS/s Calibration-Free SAR ADC
AU - Hsu, Chung Wei
AU - Chang, Soon Jyh
AU - Huang, Chun Po
AU - Chang, Li Jen
AU - Shyu, Ya Ting
AU - Hou, Chih Huei
AU - Tseng, Hwa An
AU - Kung, Chih Yuan
AU - Hu, Huan Jui
PY - 2018/3
Y1 - 2018/3
N2 - This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.
AB - This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.
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U2 - 10.1109/TCSI.2017.2771364
DO - 10.1109/TCSI.2017.2771364
M3 - Article
AN - SCOPUS:85037553635
VL - 65
SP - 881
EP - 890
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1057-7122
IS - 3
ER -