@article{b91c94277df54cf39fdc43c0d4412682,
title = "A 12-b 40-MS/s Calibration-Free SAR ADC",
abstract = "This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.",
author = "Hsu, {Chung Wei} and Chang, {Soon Jyh} and Huang, {Chun Po} and Chang, {Li Jen} and Shyu, {Ya Ting} and Hou, {Chih Huei} and Tseng, {Hwa An} and Kung, {Chih Yuan} and Hu, {Huan Jui}",
note = "Funding Information: Manuscript received June 9, 2017; revised August 30, 2017 and September 26, 2017; accepted October 31, 2017. Date of publication December 4, 2017; date of current version February 15, 2018. This work was supported by the Ministry of Science and Technology, Taiwan, under Grant MOST 105-2221-E-006-240-MY3. This paper was recommended by Associate Editor F. Lustenberger. (Corresponding author: Chung-Wei Hsu.) The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: moonfox@ sscas.ee.ncku.edu.tw; soon@mail.ncku.edu.tw). Publisher Copyright: {\textcopyright} 2017 IEEE.",
year = "2018",
month = mar,
doi = "10.1109/TCSI.2017.2771364",
language = "English",
volume = "65",
pages = "881--890",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1057-7122",
number = "3",
}