A 12-b 40-MS/s Calibration-Free SAR ADC

Chung Wei Hsu, Soon Jyh Chang, Chun Po Huang, Li Jen Chang, Ya Ting Shyu, Chih Huei Hou, Hwa An Tseng, Chih Yuan Kung, Huan Jui Hu

研究成果: Article同行評審

12 引文 斯高帕斯(Scopus)

摘要

This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.

原文English
頁(從 - 到)881-890
頁數10
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
65
發行號3
DOIs
出版狀態Published - 2018 三月

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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