摘要
In this design, a low-power incremental ADC employing the loading-free architecture for the extended counting technique is proposed. The proposed topology uses a multi-bit SAR ADC to complete the extended counting conversion, but the integrator of the preceding incremental ADC is not loaded by the DAC array of the SAR ADC, which means the opamp power can be reduced. This work adopts an incremental ADC to convert the first 5-bit MSB and a synchronous SAR ADC to convert the last 7-bit LSB, and thus totally 12-bit resolution can be obtained without calibration. The proposed topology is capable of achieving high resolution, and furthermore holds the power efficient advantage of SAR ADCs. The proposed ADC is implemented in a 0.18-μm 1P6M CMOS process. Under 4-kHz input signal bandwidth and 23.07-μW power consumption, the peak signal-to-noise and distortion ratio is 69.38 dB. The active core area including clock generator occupies of 0.33 mm2.
| 原文 | English |
|---|---|
| 頁面 | 29-32 |
| 頁數 | 4 |
| DOIs | |
| 出版狀態 | Published - 2013 五月 27 |
| 事件 | 2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013 - Kaohsiung, Taiwan 持續時間: 2013 二月 25 → 2013 二月 26 |
Other
| Other | 2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013 |
|---|---|
| 國家 | Taiwan |
| 城市 | Kaohsiung |
| 期間 | 13-02-25 → 13-02-26 |
指紋
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
引用此文
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A 12-bit 4-kHz incremental ADC with loading-free extended counting technique. / Chao, I. Jen; Huang, Chia Chun; Wu, Ying Cheng; Liu, Bin-Da; Huang, Chun Yueh; Lin, Jai-Ming.
2013. 29-32 論文發表於 2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013, Kaohsiung, Taiwan.研究成果: Paper
TY - CONF
T1 - A 12-bit 4-kHz incremental ADC with loading-free extended counting technique
AU - Chao, I. Jen
AU - Huang, Chia Chun
AU - Wu, Ying Cheng
AU - Liu, Bin-Da
AU - Huang, Chun Yueh
AU - Lin, Jai-Ming
PY - 2013/5/27
Y1 - 2013/5/27
N2 - In this design, a low-power incremental ADC employing the loading-free architecture for the extended counting technique is proposed. The proposed topology uses a multi-bit SAR ADC to complete the extended counting conversion, but the integrator of the preceding incremental ADC is not loaded by the DAC array of the SAR ADC, which means the opamp power can be reduced. This work adopts an incremental ADC to convert the first 5-bit MSB and a synchronous SAR ADC to convert the last 7-bit LSB, and thus totally 12-bit resolution can be obtained without calibration. The proposed topology is capable of achieving high resolution, and furthermore holds the power efficient advantage of SAR ADCs. The proposed ADC is implemented in a 0.18-μm 1P6M CMOS process. Under 4-kHz input signal bandwidth and 23.07-μW power consumption, the peak signal-to-noise and distortion ratio is 69.38 dB. The active core area including clock generator occupies of 0.33 mm2.
AB - In this design, a low-power incremental ADC employing the loading-free architecture for the extended counting technique is proposed. The proposed topology uses a multi-bit SAR ADC to complete the extended counting conversion, but the integrator of the preceding incremental ADC is not loaded by the DAC array of the SAR ADC, which means the opamp power can be reduced. This work adopts an incremental ADC to convert the first 5-bit MSB and a synchronous SAR ADC to convert the last 7-bit LSB, and thus totally 12-bit resolution can be obtained without calibration. The proposed topology is capable of achieving high resolution, and furthermore holds the power efficient advantage of SAR ADCs. The proposed ADC is implemented in a 0.18-μm 1P6M CMOS process. Under 4-kHz input signal bandwidth and 23.07-μW power consumption, the peak signal-to-noise and distortion ratio is 69.38 dB. The active core area including clock generator occupies of 0.33 mm2.
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U2 - 10.1109/ISNE.2013.6512278
DO - 10.1109/ISNE.2013.6512278
M3 - Paper
AN - SCOPUS:84877968942
SP - 29
EP - 32
ER -