A 12-bit 40-MS/s calibration-free SAR ADC

Chung Wei Hsu, Li Jen Chang, Chun Po Huang, Soon Jyh Chang

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

This paper presents a new circuit technique named as residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise-and-distortion ratios (SNDRs) are 66.84 dB and 69.78 dB, respectively.

原文English
主出版物標題IEEE International Symposium on Circuits and Systems
主出版物子標題From Dreams to Innovation, ISCAS 2017 - Conference Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467368520
DOIs
出版狀態Published - 2017 九月 25
事件50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
持續時間: 2017 五月 282017 五月 31

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
國家United States
城市Baltimore
期間17-05-2817-05-31

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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