摘要
Split analog-to-digital converter (ADC) digital background calibration with full-input-range error detection schemes is proposed to rapidly correct the gain and nonlinearity errors in the multi-bit first stage of a multi-channel time-interleaved (TI) pipelined ADC. By adding a vertical shift between the residue transfer curves of the first stages in two half-ADCs which are split from a single ADC, the error detection schemes of the proposed calibration are effective in the full-input range. The larger error detection range means that calibration is activated more often, resulting in fewer ADC conversions to converge. In addition, the designed fast-settling switch controller enables a 12-bit resistor-ladder DAC (R-DAC) for high-speed application. Furthermore, by applying the proposed calibration and sharing the R-DAC among all channels, the need for gain mismatch calibration between interleaved channels is eliminated. Consequently, the calibration time and complexity are further reduced. A 12-bit 400-MS/s 4-channel TI pipelined ADC prototype is implemented in 40-nm CMOS technology with an active area of 0.71 mm2, the measured SNDR and INL of which are improved up to 23 dB and 96 LSB via the proposed calibration. Compared with prior-art ADCs using background calibration, the proposed ADC achieves the fastest background calibration in 4,000 conversions/channel, which is at least 5× less than the others.
| 原文 | English |
|---|---|
| 文章編號 | 8631012 |
| 頁（從 - 到） | 1810-1814 |
| 頁數 | 5 |
| 期刊 | IEEE Transactions on Circuits and Systems II: Express Briefs |
| 卷 | 66 |
| 發行號 | 11 |
| DOIs | |
| 出版狀態 | Published - 2019 十一月 |
指紋
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
引用此文
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A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC with Split-ADC Digital Background Calibration in 4,000 Conversions/Channel. / Hung, Tsung Chih; Liao, Fan Wei; Kuo, Tai Haur.
於: IEEE Transactions on Circuits and Systems II: Express Briefs, 卷 66, 編號 11, 8631012, 11.2019, p. 1810-1814.研究成果: Article
TY - JOUR
T1 - A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC with Split-ADC Digital Background Calibration in 4,000 Conversions/Channel
AU - Hung, Tsung Chih
AU - Liao, Fan Wei
AU - Kuo, Tai Haur
PY - 2019/11
Y1 - 2019/11
N2 - Split analog-to-digital converter (ADC) digital background calibration with full-input-range error detection schemes is proposed to rapidly correct the gain and nonlinearity errors in the multi-bit first stage of a multi-channel time-interleaved (TI) pipelined ADC. By adding a vertical shift between the residue transfer curves of the first stages in two half-ADCs which are split from a single ADC, the error detection schemes of the proposed calibration are effective in the full-input range. The larger error detection range means that calibration is activated more often, resulting in fewer ADC conversions to converge. In addition, the designed fast-settling switch controller enables a 12-bit resistor-ladder DAC (R-DAC) for high-speed application. Furthermore, by applying the proposed calibration and sharing the R-DAC among all channels, the need for gain mismatch calibration between interleaved channels is eliminated. Consequently, the calibration time and complexity are further reduced. A 12-bit 400-MS/s 4-channel TI pipelined ADC prototype is implemented in 40-nm CMOS technology with an active area of 0.71 mm2, the measured SNDR and INL of which are improved up to 23 dB and 96 LSB via the proposed calibration. Compared with prior-art ADCs using background calibration, the proposed ADC achieves the fastest background calibration in 4,000 conversions/channel, which is at least 5× less than the others.
AB - Split analog-to-digital converter (ADC) digital background calibration with full-input-range error detection schemes is proposed to rapidly correct the gain and nonlinearity errors in the multi-bit first stage of a multi-channel time-interleaved (TI) pipelined ADC. By adding a vertical shift between the residue transfer curves of the first stages in two half-ADCs which are split from a single ADC, the error detection schemes of the proposed calibration are effective in the full-input range. The larger error detection range means that calibration is activated more often, resulting in fewer ADC conversions to converge. In addition, the designed fast-settling switch controller enables a 12-bit resistor-ladder DAC (R-DAC) for high-speed application. Furthermore, by applying the proposed calibration and sharing the R-DAC among all channels, the need for gain mismatch calibration between interleaved channels is eliminated. Consequently, the calibration time and complexity are further reduced. A 12-bit 400-MS/s 4-channel TI pipelined ADC prototype is implemented in 40-nm CMOS technology with an active area of 0.71 mm2, the measured SNDR and INL of which are improved up to 23 dB and 96 LSB via the proposed calibration. Compared with prior-art ADCs using background calibration, the proposed ADC achieves the fastest background calibration in 4,000 conversions/channel, which is at least 5× less than the others.
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U2 - 10.1109/TCSII.2019.2895694
DO - 10.1109/TCSII.2019.2895694
M3 - Article
AN - SCOPUS:85074485155
VL - 66
SP - 1810
EP - 1814
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-7747
IS - 11
M1 - 8631012
ER -