Class-D audio amplifiers have gradually become standard components in mobile devices, where better audio quality over a wide volume range and higher output power (P_OUT) are desired. However, in mobile devices, the P_OUT is limited since Li-ion batteries operate at 3 to 4.2V. To increase P_OUT, prior publications - have developed embedded boost converters to regulate boosted supply voltage V_PVDD to 5V or higher for the Class-D power stage at the expense of efficiency degradation. The top of Fig. 31.3.1 shows a typical digital-input open-loop Class-D audio amplifier, where the boost converter is operated only when high P_OUT is required. The input signal is first multiplied by the digital volume level, and then processed by an interpolator and a delta-sigma modulator (DSM) to achieve a high signal-to-quantization-noise ratio (SQNR). Next, the DSM output is converted into a PWM signal with a 384kHz switching frequency f_SW, Class) by the PCM-to-PWM converter to drive the power stage. The bottom of Fig. 31.3.1 illustrates the dominant factors of the THD+N in different P_OUT regions. In the low-P_OUT region, to achieve a high dynamic range (DR), the DSM loop order should be sufficiently high for more aggressive noise-shaping ability so as to suppress the DSM-shaped quantization noise. However, this tends to overload the DSM's quantizer when the DSM input is close to full scale, resulting in a rapidly increasing THD+N due to the clipping error in the high-P_OUT region. As such, the maximum P_OUT with THD+N<1 % is decreased, which squanders the boosted V_PVDD. In addition to the DSM-shaped noise, the PCM-to-PWM converter's clock (CLK) jitter noise is more significant when PWM pulses are narrower in the low-P_OUT region. As for the medium-P_OUT region, where the minimum THD+N is usually located, the THD+N is dominated by the Class-D power-stage nonlinearities.