A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-Voltage-Scaling Volume Control and Series-Connected DSM

Wei Hao Sun, Shih Hsiung Chien, Tai Haur Kuo

研究成果: Conference contribution

摘要

Class-D audio amplifiers have gradually become standard components in mobile devices, where better audio quality over a wide volume range and higher output power (P_OUT) are desired. However, in mobile devices, the P_OUT is limited since Li-ion batteries operate at 3 to 4.2V. To increase P_OUT, prior publications [1]-[3] have developed embedded boost converters to regulate boosted supply voltage V_PVDD to 5V or higher for the Class-D power stage at the expense of efficiency degradation. The top of Fig. 31.3.1 shows a typical digital-input open-loop Class-D audio amplifier, where the boost converter is operated only when high P_OUT is required. The input signal is first multiplied by the digital volume level, and then processed by an interpolator and a delta-sigma modulator (DSM) to achieve a high signal-to-quantization-noise ratio (SQNR). Next, the DSM output is converted into a PWM signal with a 384kHz switching frequency f_SW, Class) by the PCM-to-PWM converter to drive the power stage. The bottom of Fig. 31.3.1 illustrates the dominant factors of the THD+N in different P_OUT regions. In the low-P_OUT region, to achieve a high dynamic range (DR), the DSM loop order should be sufficiently high for more aggressive noise-shaping ability so as to suppress the DSM-shaped quantization noise. However, this tends to overload the DSM's quantizer when the DSM input is close to full scale, resulting in a rapidly increasing THD+N due to the clipping error in the high-P_OUT region. As such, the maximum P_OUT with THD+N<1 % is decreased, which squanders the boosted V_PVDD. In addition to the DSM-shaped noise, the PCM-to-PWM converter's clock (CLK) jitter noise is more significant when PWM pulses are narrower in the low-P_OUT region. As for the medium-P_OUT region, where the minimum THD+N is usually located, the THD+N is dominated by the Class-D power-stage nonlinearities.

原文English
主出版物標題2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
發行者Institute of Electrical and Electronics Engineers Inc.
頁面486-488
頁數3
ISBN(電子)9781665428002
DOIs
出版狀態Published - 2022
事件2022 IEEE International Solid-State Circuits Conference, ISSCC 2022 - San Francisco, United States
持續時間: 2022 2月 202022 2月 26

出版系列

名字Digest of Technical Papers - IEEE International Solid-State Circuits Conference
2022-February
ISSN(列印)0193-6530

Conference

Conference2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
國家/地區United States
城市San Francisco
期間22-02-2022-02-26

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程

指紋

深入研究「A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-Voltage-Scaling Volume Control and Series-Connected DSM」主題。共同形成了獨特的指紋。

引用此