A 14-bit low power 2-ms/s sar adc with residue oversampling*

Sheng Wen Huang, Li Jen Chang, Soon Jyh Chang

研究成果: Article同行評審

摘要

This paper presents a 2-MS/s 14-bit successive-approximation register (SAR) analog-to-digital converter (ADC) in 40 nm CMOS technology. For high resolution and low power requirements, the ADC adopts residue oversampling and Detect-and-Skip (DAS) techniques. Residue oversampling is able to reduce capacitor mismatch and noise. Therefore, the integral nonlinearity (INL), and differential nonlinearity (DNL) are diminished, and signal-to-noise ratio (SNDR) is enhanced. Besides, Detect-and-Skip (DAS) is adopted to decrease capacitor switching power and capacitor mismatch. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 2-MS/s sampling rates and 100-kS/s input frequency, the measured SNDR is 68.04dB. Static performance shows that DNL and INL are +2.31/-0.92 and +3.67/-3.92LSB, re-spectively.

原文English
頁(從 - 到)105-114
頁數10
期刊International Journal of Electrical Engineering
27
發行號3
DOIs
出版狀態Published - 2020 六月

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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