A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique

Jia Ching Wang, Tsung Chih Hung, Tai Haur Kuo

研究成果: Conference contribution

摘要

This paper presents a 15-bit pipelined ADC using the averaging correlated level shifting (Averaging-CLS) technique for reducing finite opamp gain error and opamp thermal noise. Adopting the Averaging-CLS technique enables an ADC to use a medium-accuracy amplifier structure in a high-resolution ADC. Furthermore, the front-end sample-and-hold amplifier (SHA) is removed to reduce power consumption and cost. The 15-bit pipelined ADC was fabricated by 90 nm CMOS. The measured peak SNDR achieves 73.7 dB at a 20 MS/s sampling rate and the ADC consumes 4.7 mW, leading to the Walden and Schreier Figure-of-Merits of 59.4 fJ/conv.-step and 167 dB, respectively.

原文English
主出版物標題2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728106557
DOIs
出版狀態Published - 2019 4月
事件2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
持續時間: 2019 4月 222019 4月 25

出版系列

名字2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
國家/地區Taiwan
城市Hsinchu
期間19-04-2219-04-25

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 安全、風險、可靠性和品質
  • 儀器
  • 電腦網路與通信
  • 硬體和架構

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