A 1.6-Gs/s 8b flash-SAR time-interleaved ADC with top-plate residue based gain calibration

Che Wei Hsu, Soon Jyh Chang

研究成果: Conference contribution

摘要

This paper presents a 4-channel 8-bit 1.6-GS/s Flash assisted SAR Time-Interleaved ADC in 40-nm CMOS. Putting all channel mismatch including offset, gain and timing-skew into consideration. Modified bootstrap circuit used to inhibit timing-skew; background offset calibration without complicated circuit performed in the analog domain. Proposed background gain calibration detects signal which correlated with gain error in SAR ADC and correct gain mismatch by simple calibration capacitor array, which only increase a little power and area overhead. Hybrid architecture has been adopted in this chip. Owing to Flash-SAR operation, single channel's speed and overall energy efficient can be promote at the same time. The calibration enhance SNDR from 34.59-dB to 44.15-dB. Moreover, this design consumes 16.76mW under 1V supply with FoM of 78.93fJ/conv-step in the measurement.

原文English
主出版物標題2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728192017
DOIs
出版狀態Published - 2021
事件53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of
持續時間: 2021 五月 222021 五月 28

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2021-May
ISSN(列印)0271-4310

Conference

Conference53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
國家/地區Korea, Republic of
城市Daegu
期間21-05-2221-05-28

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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