This paper presents a 4-channel 8-bit 1.6-GS/s Flash assisted SAR Time-Interleaved ADC in 40-nm CMOS. Putting all channel mismatch including offset, gain and timing-skew into consideration. Modified bootstrap circuit used to inhibit timing-skew; background offset calibration without complicated circuit performed in the analog domain. Proposed background gain calibration detects signal which correlated with gain error in SAR ADC and correct gain mismatch by simple calibration capacitor array, which only increase a little power and area overhead. Hybrid architecture has been adopted in this chip. Owing to Flash-SAR operation, single channel's speed and overall energy efficient can be promote at the same time. The calibration enhance SNDR from 34.59-dB to 44.15-dB. Moreover, this design consumes 16.76mW under 1V supply with FoM of 78.93fJ/conv-step in the measurement.