A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications

Anh Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo, Jia Hao Cheong, Xiaodan Zou, Lei Yao, Kuang-Wei Cheng, Minkyu Je

研究成果: Conference contribution

8 引文 (Scopus)

摘要

This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.

原文English
主出版物標題2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
頁面525-528
頁數4
DOIs
出版狀態Published - 2012 十一月 7
事件2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012 - Montreal, QC, Canada
持續時間: 2012 六月 172012 六月 20

出版系列

名字2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012

Other

Other2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
國家Canada
城市Montreal, QC
期間12-06-1712-06-20

指紋

Digital signal processing
Transistors
Electric power utilization
Sampling
Electric potential

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Control and Systems Engineering

引用此文

Do, A. T., Lam, C. K., Tan, Y. S., Yeo, K. S., Cheong, J. H., Zou, X., ... Je, M. (2012). A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. 於 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012 (頁 525-528). [6329072] (2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012). https://doi.org/10.1109/NEWCAS.2012.6329072
Do, Anh Tuan ; Lam, Chun Kit ; Tan, Yung Sern ; Yeo, Kiat Seng ; Cheong, Jia Hao ; Zou, Xiaodan ; Yao, Lei ; Cheng, Kuang-Wei ; Je, Minkyu. / A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012. 2012. 頁 525-528 (2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012).
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abstract = "This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.",
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Do, AT, Lam, CK, Tan, YS, Yeo, KS, Cheong, JH, Zou, X, Yao, L, Cheng, K-W & Je, M 2012, A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. 於 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012., 6329072, 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012, 頁 525-528, 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012, Montreal, QC, Canada, 12-06-17. https://doi.org/10.1109/NEWCAS.2012.6329072

A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. / Do, Anh Tuan; Lam, Chun Kit; Tan, Yung Sern; Yeo, Kiat Seng; Cheong, Jia Hao; Zou, Xiaodan; Yao, Lei; Cheng, Kuang-Wei; Je, Minkyu.

2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012. 2012. p. 525-528 6329072 (2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012).

研究成果: Conference contribution

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AU - Zou, Xiaodan

AU - Yao, Lei

AU - Cheng, Kuang-Wei

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N2 - This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.

AB - This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.

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Do AT, Lam CK, Tan YS, Yeo KS, Cheong JH, Zou X 等. A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. 於 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012. 2012. p. 525-528. 6329072. (2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012). https://doi.org/10.1109/NEWCAS.2012.6329072