A 16Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

Rizwan Bashirullah, Wentai Liu, Ralph Cavin, Dale Edwards

研究成果: Paper同行評審

9 引文 斯高帕斯(Scopus)

摘要

An adaptive bandwidth bus (ABB) uses both current and voltage sensing techniques to improve interconnection delay and signaling bandwidth compared to conventional static busses. Attaining a maximum aggregate bandwidth of 16Gb/s (i.e. 1Gb/s per line) across lossy on-chip interconnects spanning 1.75cm in length, the bus core fabricated in TSMC 0.35μm CMOS technology dissipates approximately 93mW with a supply of 2.5V and signal activity of 0.5. Experimental results indicate a reduction in power of 50% over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltagemode (VM) sensing, respectively.

原文English
頁面392-393
頁數2
出版狀態Published - 2004
事件2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States
持續時間: 2004 6月 172004 6月 19

Conference

Conference2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
國家/地區United States
城市Honolulu, HI
期間04-06-1704-06-19

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程

指紋

深入研究「A 16Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling」主題。共同形成了獨特的指紋。

引用此