TY - GEN
T1 - A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < -77dBc IM3
AU - Huang, Hung Yi
AU - Chen, Xin Yu
AU - Kuo, Tai Haur
N1 - Funding Information:
The authors would like to acknowledge the chip fabrication support provided by Taiwan Semiconductor Research Institute (TSRI), Taiwan.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/6
Y1 - 2020/6
N2 - This work presents a 14-bit 10GS/s NRZ DAC in 28nm CMOS. Using the proposed switching-glitch compensation to reduce both the switching-glitch effect and code-dependent supply bouncing, this work achieves > 64dBc SFDR and < -77 dBc IM3 over the entire Nyquist band at 10GS/s. Compared with other state-of-the-art CMOS Nyquist NRZ DACs with resolution ≥ 10bits and fs ≥ 6GHz, this work has the smallest area of 0.1mm2, the lowest power consumption of 177mW, and the best FoM performance.
AB - This work presents a 14-bit 10GS/s NRZ DAC in 28nm CMOS. Using the proposed switching-glitch compensation to reduce both the switching-glitch effect and code-dependent supply bouncing, this work achieves > 64dBc SFDR and < -77 dBc IM3 over the entire Nyquist band at 10GS/s. Compared with other state-of-the-art CMOS Nyquist NRZ DACs with resolution ≥ 10bits and fs ≥ 6GHz, this work has the smallest area of 0.1mm2, the lowest power consumption of 177mW, and the best FoM performance.
UR - http://www.scopus.com/inward/record.url?scp=85090244462&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85090244462&partnerID=8YFLogxK
U2 - 10.1109/VLSICircuits18222.2020.9162931
DO - 10.1109/VLSICircuits18222.2020.9162931
M3 - Conference contribution
AN - SCOPUS:85090244462
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
BT - 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020
Y2 - 16 June 2020 through 19 June 2020
ER -