A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS

Chun Cheng Liu, Soon-Jyh Chang, Guan Ying Huang, Ying Zu Lin, Chung-Ming Huang

研究成果: Conference contribution

99 引文 (Scopus)

摘要

This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.

原文English
主出版物標題2010 Symposium on VLSI Circuits, VLSIC 2010
頁面241-242
頁數2
DOIs
出版狀態Published - 2010 十月 22
事件2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States
持續時間: 2010 六月 162010 六月 18

出版系列

名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2010 24th Symposium on VLSI Circuits, VLSIC 2010
國家United States
城市Honolulu, HI
期間10-06-1610-06-18

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

Liu, C. C., Chang, S-J., Huang, G. Y., Lin, Y. Z., & Huang, C-M. (2010). A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS. 於 2010 Symposium on VLSI Circuits, VLSIC 2010 (頁 241-242). [5560283] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2010.5560283
Liu, Chun Cheng ; Chang, Soon-Jyh ; Huang, Guan Ying ; Lin, Ying Zu ; Huang, Chung-Ming. / A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS. 2010 Symposium on VLSI Circuits, VLSIC 2010. 2010. 頁 241-242 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).
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abstract = "This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.",
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Liu, CC, Chang, S-J, Huang, GY, Lin, YZ & Huang, C-M 2010, A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS. 於 2010 Symposium on VLSI Circuits, VLSIC 2010., 5560283, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 頁 241-242, 2010 24th Symposium on VLSI Circuits, VLSIC 2010, Honolulu, HI, United States, 10-06-16. https://doi.org/10.1109/VLSIC.2010.5560283

A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS. / Liu, Chun Cheng; Chang, Soon-Jyh; Huang, Guan Ying; Lin, Ying Zu; Huang, Chung-Ming.

2010 Symposium on VLSI Circuits, VLSIC 2010. 2010. p. 241-242 5560283 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

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AB - This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.

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Liu CC, Chang S-J, Huang GY, Lin YZ, Huang C-M. A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS. 於 2010 Symposium on VLSI Circuits, VLSIC 2010. 2010. p. 241-242. 5560283. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2010.5560283