A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS

Chun Cheng Liu; Soon-Jyh Chang; Guan Ying Huang; Ying Zu Lin; Chung-Ming Huang

doi:10.1109/VLSIC.2010.5560283

A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS

Chun Cheng Liu, Soon-Jyh Chang, Guan Ying Huang, Ying Zu Lin, Chung-Ming Huang

研究成果: Conference contribution

147 引文斯高帕斯（Scopus）

摘要

This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.

原文	English
主出版物標題	2010 Symposium on VLSI Circuits, VLSIC 2010
頁面	241-242
頁數	2
DOIs	https://doi.org/10.1109/VLSIC.2010.5560283
出版狀態	Published - 2010 10月 22
事件	2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States 持續時間: 2010 6月 16 → 2010 6月 18

出版系列

名字	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2010 24th Symposium on VLSI Circuits, VLSIC 2010
國家/地區	United States
城市	Honolulu, HI
期間	10-06-16 → 10-06-18

All Science Journal Classification (ASJC) codes

電子、光磁材料
電氣與電子工程

存取文件

10.1109/VLSIC.2010.5560283

其它文件與鏈接

引用此

@inproceedings{75b073bd06eb441eb56be432450f5fbf,

title = "A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS",

abstract = "This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.",

author = "Liu, {Chun Cheng} and Soon-Jyh Chang and Huang, {Guan Ying} and Lin, {Ying Zu} and Chung-Ming Huang",

year = "2010",

month = oct,

day = "22",

doi = "10.1109/VLSIC.2010.5560283",

language = "English",

isbn = "9781424476367",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "241--242",

booktitle = "2010 Symposium on VLSI Circuits, VLSIC 2010",

note = "2010 24th Symposium on VLSI Circuits, VLSIC 2010 ; Conference date: 16-06-2010 Through 18-06-2010",

}

Liu, CC, Chang, S-J, Huang, GY, Lin, YZ & Huang, C-M 2010, A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS. 於 2010 Symposium on VLSI Circuits, VLSIC 2010., 5560283, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 頁 241-242, 2010 24th Symposium on VLSI Circuits, VLSIC 2010, Honolulu, HI, United States, 10-06-16. https://doi.org/10.1109/VLSIC.2010.5560283

TY - GEN

T1 - A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS

AU - Liu, Chun Cheng

AU - Chang, Soon-Jyh

AU - Huang, Guan Ying

AU - Lin, Ying Zu

AU - Huang, Chung-Ming

PY - 2010/10/22

Y1 - 2010/10/22

N2 - This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.

AB - This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=77957982668&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77957982668&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2010.5560283

DO - 10.1109/VLSIC.2010.5560283

M3 - Conference contribution

AN - SCOPUS:77957982668

SN - 9781424476367

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 241

EP - 242

BT - 2010 Symposium on VLSI Circuits, VLSIC 2010

T2 - 2010 24th Symposium on VLSI Circuits, VLSIC 2010

Y2 - 16 June 2010 through 18 June 2010

ER -