A 2-D Calibration Scheme for Resistive Nonvolatile Memories

Albert Lee, Raahul Jagannathan, Di Wu, Kang L. Wang

研究成果: Article同行評審

摘要

Resistive nonvolatile memories (NVMs) promise significant performance improvement over existing NVM candidates. However, fabrication nonidealities and parasitics on the access path cause cell location-dependent variations in the total resistance received at the read circuitry. Write characteristics delivered to each cell, as well as the optimal write conditions for each cell, are also location-dependent. In this article, we propose a 2-D calibration scheme to address these variations. The proposed scheme joins row and column calibrations to create a correction grid at each crosspoint on the array and effectively cancels many spatial patterns. The enabling circuit and algorithmic modifications are described. We assess the 2-D calibration scheme in a 28-nm $256\times 256$ memory array, and show reduction in variability across multiple gradient patterns compared to conventional calibration methods. For the same calibration granularity, 2-D calibration achieves between 41% and 99% improvement depending on the amount of calibration bits. For the same amount of total calibration bits, the 2-D calibration scheme reduces the variability between 39% and 99%.

原文English
文章編號9032316
頁(從 - 到)1371-1377
頁數7
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
28
發行號6
DOIs
出版狀態Published - 2020 六月

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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