TY - JOUR
T1 - A 2-D Calibration Scheme for Resistive Nonvolatile Memories
AU - Lee, Albert
AU - Jagannathan, Raahul
AU - Wu, Di
AU - Wang, Kang L.
N1 - Funding Information:
Manuscript received November 14, 2019; revised January 23, 2020; accepted February 11, 2020. Date of publication March 11, 2020; date of current version June 1, 2020. This work was supported in part by the Air Force Research Laboratory (AFRL) and the Defense Advanced Research Projects Agency (DARPA) under Grant FA8650-18-2-7867, and in part by the National Science Foundation under Grant 1935362. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes not withstanding any copyright notation thereon. (Corresponding author: Albert Lee.) Albert Lee and Di Wu are with the Electrical Engineering Department, University of California at Los Angeles, Los Angeles, CA 90095 USA, and also with Inston Inc., Los Angeles, CA 90095 USA (e-mail: alee0618@ucla.edu).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2020/6
Y1 - 2020/6
N2 - Resistive nonvolatile memories (NVMs) promise significant performance improvement over existing NVM candidates. However, fabrication nonidealities and parasitics on the access path cause cell location-dependent variations in the total resistance received at the read circuitry. Write characteristics delivered to each cell, as well as the optimal write conditions for each cell, are also location-dependent. In this article, we propose a 2-D calibration scheme to address these variations. The proposed scheme joins row and column calibrations to create a correction grid at each crosspoint on the array and effectively cancels many spatial patterns. The enabling circuit and algorithmic modifications are described. We assess the 2-D calibration scheme in a 28-nm $256\times 256$ memory array, and show reduction in variability across multiple gradient patterns compared to conventional calibration methods. For the same calibration granularity, 2-D calibration achieves between 41% and 99% improvement depending on the amount of calibration bits. For the same amount of total calibration bits, the 2-D calibration scheme reduces the variability between 39% and 99%.
AB - Resistive nonvolatile memories (NVMs) promise significant performance improvement over existing NVM candidates. However, fabrication nonidealities and parasitics on the access path cause cell location-dependent variations in the total resistance received at the read circuitry. Write characteristics delivered to each cell, as well as the optimal write conditions for each cell, are also location-dependent. In this article, we propose a 2-D calibration scheme to address these variations. The proposed scheme joins row and column calibrations to create a correction grid at each crosspoint on the array and effectively cancels many spatial patterns. The enabling circuit and algorithmic modifications are described. We assess the 2-D calibration scheme in a 28-nm $256\times 256$ memory array, and show reduction in variability across multiple gradient patterns compared to conventional calibration methods. For the same calibration granularity, 2-D calibration achieves between 41% and 99% improvement depending on the amount of calibration bits. For the same amount of total calibration bits, the 2-D calibration scheme reduces the variability between 39% and 99%.
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U2 - 10.1109/TVLSI.2020.2975589
DO - 10.1109/TVLSI.2020.2975589
M3 - Article
AN - SCOPUS:85085924185
SN - 1063-8210
VL - 28
SP - 1371
EP - 1377
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 6
M1 - 9032316
ER -