A 2-gs/s 6-bit flash adc with offset calibration

Ying Zu Lin, Cheng Wu Lin, Soon-Jyh Chang

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

摘要

A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-μm CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed ADC. To reduce power consumption, the utilized current-mode flip-flops change their operation mode depending on the sampling rate. A simple detector composed of an inverter and a diode-connected transistor senses the clock rate. This ADC consumes 170 mW from a 1.2-V supply in high-speed mode. The maximum operation speed of this ADC achieves 3.4 GS/s when the input frequency is low. When operating at 2 GS/s, its ENOB is 5.11 bit and ERBW is 650 MHz. The proposed ADC achieves an FOM of 3.79 pJ/conversion-step at 2 GS/s.

原文English
主出版物標題Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
頁面385-388
頁數4
DOIs
出版狀態Published - 2008 十二月 1
事件2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
持續時間: 2008 十一月 32008 十一月 5

出版系列

名字Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
國家/地區Japan
城市Fukuoka
期間08-11-0308-11-05

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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