A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-μm CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed ADC. To reduce power consumption, the utilized current-mode flip-flops change their operation mode depending on the sampling rate. A simple detector composed of an inverter and a diode-connected transistor senses the clock rate. This ADC consumes 170 mW from a 1.2-V supply in high-speed mode. The maximum operation speed of this ADC achieves 3.4 GS/s when the input frequency is low. When operating at 2 GS/s, its ENOB is 5.11 bit and ERBW is 650 MHz. The proposed ADC achieves an FOM of 3.79 pJ/conversion-step at 2 GS/s.