摘要
This paper presents a 4x-interleaved 8b 2-GS/s Flash-SAR ADC in 40-nm CMOS. Instead of adding complicated circuits to calibrate offset in the background, we proposed a “top-plate swapping” technique, which only requires a low complexity circuit, to deal with offset mismatches among the channels. With the aid of the Flash ADC, a single channel can achieve 500MS/s. Proper redundancy is manipulated to deal with gain mismatches and comparator offsets among the Flash ADC and the SAR sub-ADCs. A global master clock is adopted to mitigate the impact of timing-skew. The proposed calibration enhances SNDR from 37.34-dB to 47.81-dB. Moreover, this design consumes 17.84mW under a 0.9V supply with a FoM of 44.41fJ/conv-step in post-layout simulation.
| 原文 | English |
|---|---|
| 主出版物標題 | 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings |
| 發行者 | Institute of Electrical and Electronics Engineers Inc. |
| ISBN（電子） | 9781728103976 |
| DOIs | |
| 出版狀態 | Published - 2019 一月 1 |
| 事件 | 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan 持續時間: 2019 五月 26 → 2019 五月 29 |
出版系列
| 名字 | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| 卷 | 2019-May |
| ISSN（列印） | 0271-4310 |
Conference
| Conference | 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 |
|---|---|
| 國家 | Japan |
| 城市 | Sapporo |
| 期間 | 19-05-26 → 19-05-29 |
指紋
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
引用此文
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A 2-GS/s 8b flash-SAR time-interleaved ADC with background offset calibration. / Cheng, Yi Shen; Hu, Huan Jui; Chang, Soon-Jyh.
2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8702543 (Proceedings - IEEE International Symposium on Circuits and Systems; 卷 2019-May).研究成果: Conference contribution
TY - GEN
T1 - A 2-GS/s 8b flash-SAR time-interleaved ADC with background offset calibration
AU - Cheng, Yi Shen
AU - Hu, Huan Jui
AU - Chang, Soon-Jyh
PY - 2019/1/1
Y1 - 2019/1/1
N2 - This paper presents a 4x-interleaved 8b 2-GS/s Flash-SAR ADC in 40-nm CMOS. Instead of adding complicated circuits to calibrate offset in the background, we proposed a “top-plate swapping” technique, which only requires a low complexity circuit, to deal with offset mismatches among the channels. With the aid of the Flash ADC, a single channel can achieve 500MS/s. Proper redundancy is manipulated to deal with gain mismatches and comparator offsets among the Flash ADC and the SAR sub-ADCs. A global master clock is adopted to mitigate the impact of timing-skew. The proposed calibration enhances SNDR from 37.34-dB to 47.81-dB. Moreover, this design consumes 17.84mW under a 0.9V supply with a FoM of 44.41fJ/conv-step in post-layout simulation.
AB - This paper presents a 4x-interleaved 8b 2-GS/s Flash-SAR ADC in 40-nm CMOS. Instead of adding complicated circuits to calibrate offset in the background, we proposed a “top-plate swapping” technique, which only requires a low complexity circuit, to deal with offset mismatches among the channels. With the aid of the Flash ADC, a single channel can achieve 500MS/s. Proper redundancy is manipulated to deal with gain mismatches and comparator offsets among the Flash ADC and the SAR sub-ADCs. A global master clock is adopted to mitigate the impact of timing-skew. The proposed calibration enhances SNDR from 37.34-dB to 47.81-dB. Moreover, this design consumes 17.84mW under a 0.9V supply with a FoM of 44.41fJ/conv-step in post-layout simulation.
UR - http://www.scopus.com/inward/record.url?scp=85066810629&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85066810629&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2019.8702543
DO - 10.1109/ISCAS.2019.8702543
M3 - Conference contribution
AN - SCOPUS:85066810629
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -