This paper presents a 4x-interleaved 8b 2-GS/s Flash-SAR ADC in 40-nm CMOS. Instead of adding complicated circuits to calibrate offset in the background, we proposed a “top-plate swapping” technique, which only requires a low complexity circuit, to deal with offset mismatches among the channels. With the aid of the Flash ADC, a single channel can achieve 500MS/s. Proper redundancy is manipulated to deal with gain mismatches and comparator offsets among the Flash ADC and the SAR sub-ADCs. A global master clock is adopted to mitigate the impact of timing-skew. The proposed calibration enhances SNDR from 37.34-dB to 47.81-dB. Moreover, this design consumes 17.84mW under a 0.9V supply with a FoM of 44.41fJ/conv-step in post-layout simulation.