A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process

Chia Hsin Lee, Chih Huei Hou, Chun Po Huang, Soon-Jyh Chang, Yuan Ta Hsieh, Ying Zong Juang

研究成果: Conference contribution

2 引文 (Scopus)

摘要

This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.

原文English
主出版物標題2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467394987
DOIs
出版狀態Published - 2016 五月 31
事件2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
持續時間: 2016 四月 252016 四月 27

出版系列

名字2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
國家Taiwan
城市Hsinchu
期間16-04-2516-04-27

指紋

registers
analog to digital converters
Digital to analog conversion
CMOS
cycles
approximation
digital to analog converters
Error correction
requirements
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation

引用此文

Lee, C. H., Hou, C. H., Huang, C. P., Chang, S-J., Hsieh, Y. T., & Juang, Y. Z. (2016). A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process. 於 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482525] (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482525
Lee, Chia Hsin ; Hou, Chih Huei ; Huang, Chun Po ; Chang, Soon-Jyh ; Hsieh, Yuan Ta ; Juang, Ying Zong. / A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process. 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).
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title = "A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process",
abstract = "This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.",
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Lee, CH, Hou, CH, Huang, CP, Chang, S-J, Hsieh, YT & Juang, YZ 2016, A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process. 於 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482525, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 16-04-25. https://doi.org/10.1109/VLSI-DAT.2016.7482525

A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process. / Lee, Chia Hsin; Hou, Chih Huei; Huang, Chun Po; Chang, Soon-Jyh; Hsieh, Yuan Ta; Juang, Ying Zong.

2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482525 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

研究成果: Conference contribution

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AU - Hou, Chih Huei

AU - Huang, Chun Po

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AU - Hsieh, Yuan Ta

AU - Juang, Ying Zong

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N2 - This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.

AB - This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.

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Lee CH, Hou CH, Huang CP, Chang S-J, Hsieh YT, Juang YZ. A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process. 於 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482525. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). https://doi.org/10.1109/VLSI-DAT.2016.7482525