A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process

Chia Hsin Lee; Chih Huei Hou; Chun Po Huang; Soon Jyh Chang; Yuan Ta Hsieh; Ying Zong Juang

doi:10.1109/VLSI-DAT.2016.7482525

A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process

Chia Hsin Lee, Chih Huei Hou, Chun Po Huang, Soon Jyh Chang, Yuan Ta Hsieh, Ying Zong Juang

電機工程學系

研究成果: Conference contribution

4 引文斯高帕斯（Scopus）

摘要

This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.

原文	English
主出版物標題	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781467394987
DOIs	https://doi.org/10.1109/VLSI-DAT.2016.7482525
出版狀態	Published - 2016 5月 31
事件	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan 持續時間: 2016 4月 25 → 2016 4月 27

出版系列

名字	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
國家/地區	Taiwan
城市	Hsinchu
期間	16-04-25 → 16-04-27

All Science Journal Classification (ASJC) codes

硬體和架構
電氣與電子工程
安全、風險、可靠性和品質
儀器

存取文件

10.1109/VLSI-DAT.2016.7482525

其它文件與鏈接

引用此

Lee, C. H., Hou, C. H., Huang, C. P., Chang, S. J., Hsieh, Y. T., & Juang, Y. Z. (2016). A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process. 於 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 文章 7482525 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482525

@inproceedings{e2977de73533431984eafab1becf245d,

title = "A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process",

abstract = "This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.",

author = "Lee, {Chia Hsin} and Hou, {Chih Huei} and Huang, {Chun Po} and Chang, {Soon Jyh} and Hsieh, {Yuan Ta} and Juang, {Ying Zong}",

note = "Funding Information: The authors would like to thank the fabrication and measurement support of Chip Implementation Center (CIC), Taiwan. This work was supported in part by the grant of MOST 104-2220-E-006-012- from Ministry of Science and Technology, Taiwan. Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 ; Conference date: 25-04-2016 Through 27-04-2016",

year = "2016",

month = may,

day = "31",

doi = "10.1109/VLSI-DAT.2016.7482525",

language = "English",

series = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

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address = "United States",

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Lee, CH, Hou, CH, Huang, CP, Chang, SJ, Hsieh, YT & Juang, YZ 2016, A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process. 於 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482525, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 16-04-25. https://doi.org/10.1109/VLSI-DAT.2016.7482525

A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process. / Lee, Chia Hsin; Hou, Chih Huei; Huang, Chun Po 等.
2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482525 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

研究成果: Conference contribution

TY - GEN

T1 - A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process

AU - Lee, Chia Hsin

AU - Hou, Chih Huei

AU - Huang, Chun Po

AU - Chang, Soon Jyh

AU - Hsieh, Yuan Ta

AU - Juang, Ying Zong

N1 - Funding Information: The authors would like to thank the fabrication and measurement support of Chip Implementation Center (CIC), Taiwan. This work was supported in part by the grant of MOST 104-2220-E-006-012- from Ministry of Science and Technology, Taiwan. Publisher Copyright: © 2016 IEEE.

PY - 2016/5/31

Y1 - 2016/5/31

N2 - This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.

AB - This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.

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DO - 10.1109/VLSI-DAT.2016.7482525

M3 - Conference contribution

AN - SCOPUS:84978413837

T3 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Y2 - 25 April 2016 through 27 April 2016

ER -

Lee CH, Hou CH, Huang CP, Chang SJ, Hsieh YT, Juang YZ. A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process. 於 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482525. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). doi: 10.1109/VLSI-DAT.2016.7482525

A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process

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