A 3-D BiCMOS technology using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE)

Mahender Kumar, Haitao Liu, Johnny K.O. Sin, Jun Wan, Kang L. Wang

研究成果: Conference article同行評審

4 引文 斯高帕斯(Scopus)

摘要

In this paper, a novel 3-D BiCMOS technology is proposed and demonstrated for the first time. To implement the 3-D BiCMOS structure, the NMOS transistors are fabricated on the bulk substrate (bottom layer), the PMOS transistors are fabricated on the single crystal top layer which is obtained using the selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE), and the BJTs are fabricated in the SEG regions. The mobility of the PMOS transistors fabricated on the top layer is only approximately 5% lower than those fabricated on SOI wafers, and the BJTs also have high performance with a peak fT of 17 GHz and a peak fmax of 14 GHz. This 3-D BiCMOS technology is very promising for low power, high speed, and high frequency integrated circuits applications.

原文English
頁(從 - 到)729-732
頁數4
期刊Technical Digest - International Electron Devices Meeting
出版狀態Published - 2001
事件IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States
持續時間: 2001 十二月 22001 十二月 5

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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