In this paper, a novel 3-D BiCMOS technology is proposed and demonstrated for the first time. To implement the 3-D BiCMOS structure, the NMOS transistors are fabricated on the bulk substrate (bottom layer), the PMOS transistors are fabricated on the single crystal top layer which is obtained using the selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE), and the BJTs are fabricated in the SEG regions. The mobility of the PMOS transistors fabricated on the top layer is only approximately 5% lower than those fabricated on SOI wafers, and the BJTs also have high performance with a peak fT of 17 GHz and a peak fmax of 14 GHz. This 3-D BiCMOS technology is very promising for low power, high speed, and high frequency integrated circuits applications.
|頁（從 - 到）||729-732|
|期刊||Technical Digest - International Electron Devices Meeting|
|出版狀態||Published - 2001|
|事件||IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States|
持續時間: 2001 12月 2 → 2001 12月 5
All Science Journal Classification (ASJC) codes