A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window

Cheng Hsun Ho, Soon Jyh Chang, Guan Ying Huang, Che Hsun Kuo

研究成果: Conference contribution

摘要

This paper proposes a 10-bit SAR ADC with time-based fixed window to reduce the unnecessary capacitor switchings, comparisons and digital control operations. It used only one comparator, and no need additional reference voltage to create the window. At 0.5-V supply and 100-kS/s, the ADC consumes only 252 nW and achieves an SNDR of 57.96 dB, resulting in a FOM of 3.9 fJ/conversion-step. The ADC core occupies an active area of only 178 × 184 μm2 in 0.18-μm CMOS process.

原文English
主出版物標題2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面2345-2348
頁數4
ISBN(列印)9781479934324
DOIs
出版狀態Published - 2014 一月 1
事件2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
持續時間: 2014 六月 12014 六月 5

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
國家Australia
城市Melbourne, VIC
期間14-06-0114-06-05

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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