@inproceedings{197314ac9c3b47259ff547a056240e48,
title = "A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window",
abstract = "This paper proposes a 10-bit SAR ADC with time-based fixed window to reduce the unnecessary capacitor switchings, comparisons and digital control operations. It used only one comparator, and no need additional reference voltage to create the window. At 0.5-V supply and 100-kS/s, the ADC consumes only 252 nW and achieves an SNDR of 57.96 dB, resulting in a FOM of 3.9 fJ/conversion-step. The ADC core occupies an active area of only 178 × 184 μm2 in 0.18-μm CMOS process.",
author = "Ho, {Cheng Hsun} and Chang, {Soon Jyh} and Huang, {Guan Ying} and Kuo, {Che Hsun}",
year = "2014",
month = jan,
day = "1",
doi = "10.1109/ISCAS.2014.6865642",
language = "English",
isbn = "9781479934324",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2345--2348",
booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",
address = "United States",
note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",
}