A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window

Cheng Hsun Ho; Soon Jyh Chang; Guan Ying Huang; Che Hsun Kuo

doi:10.1109/ISCAS.2014.6865642

A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window

Cheng Hsun Ho, Soon Jyh Chang, Guan Ying Huang, Che Hsun Kuo

電機工程學系

研究成果: Conference contribution

摘要

This paper proposes a 10-bit SAR ADC with time-based fixed window to reduce the unnecessary capacitor switchings, comparisons and digital control operations. It used only one comparator, and no need additional reference voltage to create the window. At 0.5-V supply and 100-kS/s, the ADC consumes only 252 nW and achieves an SNDR of 57.96 dB, resulting in a FOM of 3.9 fJ/conversion-step. The ADC core occupies an active area of only 178 × 184 μm² in 0.18-μm CMOS process.

原文	English
主出版物標題	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	2345-2348
頁數	4
ISBN（列印）	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865642
出版狀態	Published - 2014 一月 1
事件	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia 持續時間: 2014 六月 1 → 2014 六月 5

出版系列

名字	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN（列印）	0271-4310

Other

Other	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
國家	Australia
城市	Melbourne, VIC
期間	14-06-01 → 14-06-05

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

存取文件

10.1109/ISCAS.2014.6865642

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引用此

Ho, C. H., Chang, S. J., Huang, G. Y., & Kuo, C. H. (2014). A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window. 於 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (頁 2345-2348). [6865642] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865642

Ho, Cheng Hsun ; Chang, Soon Jyh ; Huang, Guan Ying ; Kuo, Che Hsun. / A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window. 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 頁 2345-2348 (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{197314ac9c3b47259ff547a056240e48,

title = "A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window",

abstract = "This paper proposes a 10-bit SAR ADC with time-based fixed window to reduce the unnecessary capacitor switchings, comparisons and digital control operations. It used only one comparator, and no need additional reference voltage to create the window. At 0.5-V supply and 100-kS/s, the ADC consumes only 252 nW and achieves an SNDR of 57.96 dB, resulting in a FOM of 3.9 fJ/conversion-step. The ADC core occupies an active area of only 178 × 184 μm2 in 0.18-μm CMOS process.",

author = "Ho, {Cheng Hsun} and Chang, {Soon Jyh} and Huang, {Guan Ying} and Kuo, {Che Hsun}",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/ISCAS.2014.6865642",

language = "English",

isbn = "9781479934324",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "2345--2348",

booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",

address = "United States",

note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",

}

Ho, CH, Chang, SJ, Huang, GY & Kuo, CH 2014, A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window. 於 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865642, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 頁 2345-2348, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 14-06-01. https://doi.org/10.1109/ISCAS.2014.6865642

A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window. / Ho, Cheng Hsun; Chang, Soon Jyh; Huang, Guan Ying; Kuo, Che Hsun.

2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 2345-2348 6865642 (Proceedings - IEEE International Symposium on Circuits and Systems).

研究成果: Conference contribution

TY - GEN

T1 - A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window

AU - Ho, Cheng Hsun

AU - Chang, Soon Jyh

AU - Huang, Guan Ying

AU - Kuo, Che Hsun

PY - 2014/1/1

Y1 - 2014/1/1

N2 - This paper proposes a 10-bit SAR ADC with time-based fixed window to reduce the unnecessary capacitor switchings, comparisons and digital control operations. It used only one comparator, and no need additional reference voltage to create the window. At 0.5-V supply and 100-kS/s, the ADC consumes only 252 nW and achieves an SNDR of 57.96 dB, resulting in a FOM of 3.9 fJ/conversion-step. The ADC core occupies an active area of only 178 × 184 μm2 in 0.18-μm CMOS process.

AB - This paper proposes a 10-bit SAR ADC with time-based fixed window to reduce the unnecessary capacitor switchings, comparisons and digital control operations. It used only one comparator, and no need additional reference voltage to create the window. At 0.5-V supply and 100-kS/s, the ADC consumes only 252 nW and achieves an SNDR of 57.96 dB, resulting in a FOM of 3.9 fJ/conversion-step. The ADC core occupies an active area of only 178 × 184 μm2 in 0.18-μm CMOS process.

UR - http://www.scopus.com/inward/record.url?scp=84907404195&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84907404195&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2014.6865642

DO - 10.1109/ISCAS.2014.6865642

M3 - Conference contribution

AN - SCOPUS:84907404195

SN - 9781479934324

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 2345

EP - 2348

BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

Y2 - 1 June 2014 through 5 June 2014

ER -

Ho CH, Chang SJ, Huang GY, Kuo CH. A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window. 於 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 2345-2348. 6865642. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2014.6865642