摘要
With the advance of CMOS technology, CPU performance has been improved by increasing frequency. However, the performance improvement for a single-core processor has reached a 60bottleneck due to chip power and heat removal limitations. To overcome these problems, chip multiprocessors (CMPs) have gradually replaced single-core processors, and the number of cores in CMPs is expected to continue to grow. A processor integrating 80 cores has been demonstrated by Intel [1]. In CMP architecture, the last level cache (LLC) is shared by multicore processors and has a significant influence on performance. Therefore, as the CMP architecture has become more widely used, LLC-related research has drawn increased attention.
| 原文 | English |
|---|---|
| 主出版物標題 | High Performance Computing for Big Data |
| 主出版物子標題 | Methodologies and Applications |
| 發行者 | CRC Press |
| 頁面 | 59-80 |
| 頁數 | 22 |
| ISBN（電子） | 9781498784009 |
| ISBN（列印） | 9781498783996 |
| DOIs | |
| 出版狀態 | Published - 2017 一月 1 |
指紋
All Science Journal Classification (ASJC) codes
- Computer Science(all)
- Economics, Econometrics and Finance(all)
- Business, Management and Accounting(all)
引用此文
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A 3D hybrid cache design for CMP architecture for data-intensive applications. / Lin, Ing-Chao; Chiou, Jeng Nian; Law, Yun Kae.
High Performance Computing for Big Data: Methodologies and Applications. CRC Press, 2017. p. 59-80.研究成果: Chapter
TY - CHAP
T1 - A 3D hybrid cache design for CMP architecture for data-intensive applications
AU - Lin, Ing-Chao
AU - Chiou, Jeng Nian
AU - Law, Yun Kae
PY - 2017/1/1
Y1 - 2017/1/1
N2 - With the advance of CMOS technology, CPU performance has been improved by increasing frequency. However, the performance improvement for a single-core processor has reached a 60bottleneck due to chip power and heat removal limitations. To overcome these problems, chip multiprocessors (CMPs) have gradually replaced single-core processors, and the number of cores in CMPs is expected to continue to grow. A processor integrating 80 cores has been demonstrated by Intel [1]. In CMP architecture, the last level cache (LLC) is shared by multicore processors and has a significant influence on performance. Therefore, as the CMP architecture has become more widely used, LLC-related research has drawn increased attention.
AB - With the advance of CMOS technology, CPU performance has been improved by increasing frequency. However, the performance improvement for a single-core processor has reached a 60bottleneck due to chip power and heat removal limitations. To overcome these problems, chip multiprocessors (CMPs) have gradually replaced single-core processors, and the number of cores in CMPs is expected to continue to grow. A processor integrating 80 cores has been demonstrated by Intel [1]. In CMP architecture, the last level cache (LLC) is shared by multicore processors and has a significant influence on performance. Therefore, as the CMP architecture has become more widely used, LLC-related research has drawn increased attention.
UR - http://www.scopus.com/inward/record.url?scp=85052681135&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85052681135&partnerID=8YFLogxK
U2 - 10.1201/b21235
DO - 10.1201/b21235
M3 - Chapter
AN - SCOPUS:85052681135
SN - 9781498783996
SP - 59
EP - 80
BT - High Performance Computing for Big Data
PB - CRC Press
ER -