A 3mW 6b 4GS/s Subranging ADC with Adaptive Offset-Adjustable Comparators

Chung Ming Yang, Tai-Haur Kuo

研究成果: Conference contribution

摘要

This work implements a 3mW 6b 4GS/s subranging ADC in 28nm CMOS. With the proposed adaptive offset-adjustable comparators (OACs), the subranging architecture is free of both conventional reference-voltage switching to increase speed and the resistor ladder to save power. A proposed calibration technique mitigates the intrinsic offset of the OACs and improves the linearity of the fine ADC in different subrange regions. At 3.6GS/s, the ADC has the best Walden FOM of 22.7fJ/conv-step compared with prior state-of-the-art ADCs.

原文English
主出版物標題2019 IEEE Custom Integrated Circuits Conference, CICC 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538693957
DOIs
出版狀態Published - 2019 四月 1
事件40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, United States
持續時間: 2019 四月 142019 四月 17

出版系列

名字Proceedings of the Custom Integrated Circuits Conference
2019-April
ISSN(列印)0886-5930

Conference

Conference40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019
國家United States
城市Austin
期間19-04-1419-04-17

指紋

Ladders
Resistors
Calibration
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

Yang, C. M., & Kuo, T-H. (2019). A 3mW 6b 4GS/s Subranging ADC with Adaptive Offset-Adjustable Comparators. 於 2019 IEEE Custom Integrated Circuits Conference, CICC 2019 [8780174] (Proceedings of the Custom Integrated Circuits Conference; 卷 2019-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2019.8780174
Yang, Chung Ming ; Kuo, Tai-Haur. / A 3mW 6b 4GS/s Subranging ADC with Adaptive Offset-Adjustable Comparators. 2019 IEEE Custom Integrated Circuits Conference, CICC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings of the Custom Integrated Circuits Conference).
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abstract = "This work implements a 3mW 6b 4GS/s subranging ADC in 28nm CMOS. With the proposed adaptive offset-adjustable comparators (OACs), the subranging architecture is free of both conventional reference-voltage switching to increase speed and the resistor ladder to save power. A proposed calibration technique mitigates the intrinsic offset of the OACs and improves the linearity of the fine ADC in different subrange regions. At 3.6GS/s, the ADC has the best Walden FOM of 22.7fJ/conv-step compared with prior state-of-the-art ADCs.",
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Yang, CM & Kuo, T-H 2019, A 3mW 6b 4GS/s Subranging ADC with Adaptive Offset-Adjustable Comparators. 於 2019 IEEE Custom Integrated Circuits Conference, CICC 2019., 8780174, Proceedings of the Custom Integrated Circuits Conference, 卷 2019-April, Institute of Electrical and Electronics Engineers Inc., 40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, United States, 19-04-14. https://doi.org/10.1109/CICC.2019.8780174

A 3mW 6b 4GS/s Subranging ADC with Adaptive Offset-Adjustable Comparators. / Yang, Chung Ming; Kuo, Tai-Haur.

2019 IEEE Custom Integrated Circuits Conference, CICC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8780174 (Proceedings of the Custom Integrated Circuits Conference; 卷 2019-April).

研究成果: Conference contribution

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N2 - This work implements a 3mW 6b 4GS/s subranging ADC in 28nm CMOS. With the proposed adaptive offset-adjustable comparators (OACs), the subranging architecture is free of both conventional reference-voltage switching to increase speed and the resistor ladder to save power. A proposed calibration technique mitigates the intrinsic offset of the OACs and improves the linearity of the fine ADC in different subrange regions. At 3.6GS/s, the ADC has the best Walden FOM of 22.7fJ/conv-step compared with prior state-of-the-art ADCs.

AB - This work implements a 3mW 6b 4GS/s subranging ADC in 28nm CMOS. With the proposed adaptive offset-adjustable comparators (OACs), the subranging architecture is free of both conventional reference-voltage switching to increase speed and the resistor ladder to save power. A proposed calibration technique mitigates the intrinsic offset of the OACs and improves the linearity of the fine ADC in different subrange regions. At 3.6GS/s, the ADC has the best Walden FOM of 22.7fJ/conv-step compared with prior state-of-the-art ADCs.

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Yang CM, Kuo T-H. A 3mW 6b 4GS/s Subranging ADC with Adaptive Offset-Adjustable Comparators. 於 2019 IEEE Custom Integrated Circuits Conference, CICC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8780174. (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2019.8780174