A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique

I. Jen Chao, Chia Ming Kuo, Bin-Da Liu, Chun Yueh Huang, Soon-Jyh Chang

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

This paper proposes a 3rd-order low-distortion delta-sigma modulator (DSM) structure, which uses the timing-sharing technique between the 2nd and 3rd integrators during one clock phase. Further, since the operation phase of the 1st integrator is different to those of the 2nd and 3rd integrators, the three integrators are realized in just single opamp by the opamp sharing. Therefore, the power consumption can be reduced greatly. Besides, the proposed DSM structure poses the feature of relaxed feedback timing. The quantization and DEM operation can be extended from a non-overlapping interval for a conventional low-distortion structure to half of the clock period. The proposed 3rd-order 4-bit DSM is implemented in a 90-nm CMOS process. Post-layout simulation shows that the modulator achieves 75.1-dB SNDR with 2.5-MHz input signal bandwidth and 80-MHz sampling frequency. The power consumption is only 1.42 mW with 61.1-fJ/conversion-step FOM, and the core area is 683 × 592 μm 2.

原文English
主出版物標題2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
頁面2002-2005
頁數4
DOIs
出版狀態Published - 2013 九月 9
事件2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
持續時間: 2013 五月 192013 五月 23

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Other

Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
國家China
城市Beijing
期間13-05-1913-05-23

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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