A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth

Tsung-chih Hung; Tai-haur Kuo

doi:10.1109/CICC.2019.8780368

A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth

Tsung-chih Hung, Tai-haur Kuo

電機工程學系

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

原文	English
頁面	1-4
DOIs	https://doi.org/10.1109/CICC.2019.8780368
出版狀態	Published - 2019 4月
事件	2019 IEEE Custom Integrated Circuits Conference (CICC) - Austin, TX, USA 持續時間: 2019 4月 14 → 2019 4月 17

Conference

Conference	2019 IEEE Custom Integrated Circuits Conference (CICC)
期間	19-04-14 → 19-04-17

存取文件

10.1109/CICC.2019.8780368

https://ieeexplore.ieee.org/document/8780368/

引用此

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