A 49.23% Power Reduction Active Gate Driver with Digital Multi-level Power Gating Control

When it comes to power systems, both overall performance and efficiency are key factors in the design of the power device drivers. Using multi-level power gating logic, this study developed an active gate driver (AGD) design that is capable of driving the power transistor at different voltage levels. To lessen the amount of power that the AGD consumes, it is equipped with an effective power gating control logic. Additionally, the Four-stage Stability Control Circuit inside of the AGD makes certain that each and every power MOS device contained within the buffer arrays of the Output Stage is equally utilized. For the implementation of the AGD design, the TSMC 180-nm High-voltage (HV) Bipolar-CMOS-DMOS (BCD) process was utilized. The measurement outcomes with C_load equal to 2 nF and an operating PWM frequency of 400 kHz validate the functionality of the AGD design. It dissipates an average of 533 mW, which is a combination of static and dynamic power. Finally, the power gating mechanism offers a power reduction of 49.23%, as determined by a comparison of two cycles with and without power gating circuit installed.