A 5-bit 1 GSample/s two-stage ADC with a new flash folded architecture

Hung Yu Huang, Ying Zu Lin, Soon Jyh Chang

研究成果: Conference contribution

5 引文 斯高帕斯(Scopus)


A 5-bit 1 GSample/s two-stage ADC is designed and simulated in TSMC 0.18-μm CMOS technology. The new architecture combines the characteristics of flash, subranging and folding ADC. The analog front-end of this work is the same as that of a typical flash ADC. By replacing folding amplifier with the current-mode multiplexer (MUX), cyclic thermometer code, the digital output of folding ADC, is obtained and frequency multiplication effect is avoided. Besides, the slow switching of the reference voltage range is also avoided. The number of the comparators is reduced to 16, and it is 32 typically. Operating at 1 GSample/s, the ENOB is 4.92 and 4.71 bit at input frequency 10 and 500 MHz, respectively. This ADC consumes 63mW from a 1.8 V supply, achieving FOMs of 2.4 pJ/conversion-step at 1 GSample/s.

主出版物標題TENCON 2007 - 2007 IEEE Region 10 Conference
出版狀態Published - 2007
事件IEEE Region 10 Conference, TENCON 2007 - Taipei, Taiwan
持續時間: 2007 10月 302007 11月 2


名字IEEE Region 10 Annual International Conference, Proceedings/TENCON


OtherIEEE Region 10 Conference, TENCON 2007

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電氣與電子工程


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