This paper presents a low-power 5-bit 1.35-GSPS current-steering digital-to-analog converter (DAC) for ultrawideband (UWB) transceivers. A "3 (thermometer) + 2 (binary)" segmented structure is used for reaching a compromise between the circuit complexity and differential nonlinearity (DNL) error. To save the power consumption while maintaining the same output voltage swing, a bipolar current source cell is employed. Besides, a de-glitch latch is presented to reduce the clock feedthrough from the pass transistors. This DAC was implemented in a standard 0.18-μm 1P6M CMOS technology. The measured integral nonlinearity (INL) and the differential nonlinearity (DNL) are less than 0.04 LSB and 0.05 LSB, respectively. The spurious-free dynamic range (SFDR) is above 30 dB over the complete Nyquist band at a sampling rate of 1.35 GHz. The power consumption of this DAC is 9.7 mW. The active area of the circuit occupies 0.19 mm2.