A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS

Ying Zu Lin, Yen Ting Liu, Soon Jyh Chang

研究成果: Conference contribution

24 引文 斯高帕斯(Scopus)

摘要

A compact 5-bit flash ADC is designed and fabricated in TSMC 0.13-μm CMOS process. Resistive averaging network and interpolation are discussed and analyzed for power reduction. This proposed ADC consumes 180 mW from a 1.2 V supply and occupies 0.16 mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.51 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.

原文English
主出版物標題Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
發行者Institute of Electrical and Electronics Engineers Inc.
頁面213-216
頁數4
ISBN(電子)1424407869, 9781424407866
DOIs
出版狀態Published - 2007 1月 1
事件29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
持續時間: 2007 9月 162007 9月 19

出版系列

名字Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
國家/地區United States
城市San Jose
期間07-09-1607-09-19

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

指紋

深入研究「A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS」主題。共同形成了獨特的指紋。

引用此