A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS process

Ying Zu Lin, Soon Jyh Chang, Yen Ting Liu

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC are specified. Based on the quantitative analysis, a compact 5-bit flash ADC is designed and fabricated in a 0.13-μm CMOS process. The proposed ADC consumes 180 mW from a 1.2-V supply and occupies 0.16-mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.59 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.

原文English
頁(從 - 到)258-268
頁數11
期刊IEICE Transactions on Electronics
E92-C
發行號2
DOIs
出版狀態Published - 2009 一月 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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