A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector

Yen Long Lee, Soon-Jyh Chang, Rong Sing Chu, Ying Zu Lin, Yen Chi Chen, Goh Jih Ren, Chung-Ming Huang

研究成果: Paper同行評審

8 引文 斯高帕斯(Scopus)

摘要

This paper presents a 5-Gb/s 1/4-rate clock and data recovery (CDR) circuit. The proposed dynamic stepwise bang-bang phase detector comprises the advantage of linear and bang-bang phase detectors. The CDR adjusts the charge pump currents and the interpolation weight of phase interpolators according to the phase error between input data and feedback clock. This CDR circuit was fabricated in TSMC 1P9M 90-nm CMOS technology. It consumes 16.8 mW from a 1.2-V supply and occupies an active area of 0.3 mm2. The measured peak-to-peak jitter and rms jitter of the recovered clock are 42.37 ps and 7.06 ps for a 5-Gb/s 27-1 PRBS, respectively. Moreover, the measured peak-to-peak jitter and rms jitter of the recovered data are 53.33 ps and 8.89 ps for a 5-Gb/s 27-1 PRBS, respectively.

原文English
頁面141-144
頁數4
DOIs
出版狀態Published - 2012 十二月 1
事件2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
持續時間: 2012 十一月 122012 十一月 14

Other

Other2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
國家Japan
城市Kobe
期間12-11-1212-11-14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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