A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector

Yen Long Lee, Soon-Jyh Chang, Rong Sing Chu, Ying Zu Lin, Yen Chi Chen, Goh Jih Ren, Chung-Ming Huang

研究成果: Paper

7 引文 (Scopus)

摘要

This paper presents a 5-Gb/s 1/4-rate clock and data recovery (CDR) circuit. The proposed dynamic stepwise bang-bang phase detector comprises the advantage of linear and bang-bang phase detectors. The CDR adjusts the charge pump currents and the interpolation weight of phase interpolators according to the phase error between input data and feedback clock. This CDR circuit was fabricated in TSMC 1P9M 90-nm CMOS technology. It consumes 16.8 mW from a 1.2-V supply and occupies an active area of 0.3 mm2. The measured peak-to-peak jitter and rms jitter of the recovered clock are 42.37 ps and 7.06 ps for a 5-Gb/s 27-1 PRBS, respectively. Moreover, the measured peak-to-peak jitter and rms jitter of the recovered data are 53.33 ps and 8.89 ps for a 5-Gb/s 27-1 PRBS, respectively.

原文English
頁面141-144
頁數4
DOIs
出版狀態Published - 2012 十二月 1
事件2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
持續時間: 2012 十一月 122012 十一月 14

Other

Other2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
國家Japan
城市Kobe
期間12-11-1212-11-14

指紋

Clock and data recovery circuits (CDR circuits)
Jitter
Detectors
Clocks
Interpolation
Pumps
Feedback
Recovery

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此文

Lee, Y. L., Chang, S-J., Chu, R. S., Lin, Y. Z., Chen, Y. C., Ren, G. J., & Huang, C-M. (2012). A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector. 141-144. 論文發表於 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012, Kobe, Japan. https://doi.org/10.1109/IPEC.2012.6522645
Lee, Yen Long ; Chang, Soon-Jyh ; Chu, Rong Sing ; Lin, Ying Zu ; Chen, Yen Chi ; Ren, Goh Jih ; Huang, Chung-Ming. / A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector. 論文發表於 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012, Kobe, Japan.4 p.
@conference{56938891eca042ef93017123f8a63449,
title = "A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector",
abstract = "This paper presents a 5-Gb/s 1/4-rate clock and data recovery (CDR) circuit. The proposed dynamic stepwise bang-bang phase detector comprises the advantage of linear and bang-bang phase detectors. The CDR adjusts the charge pump currents and the interpolation weight of phase interpolators according to the phase error between input data and feedback clock. This CDR circuit was fabricated in TSMC 1P9M 90-nm CMOS technology. It consumes 16.8 mW from a 1.2-V supply and occupies an active area of 0.3 mm2. The measured peak-to-peak jitter and rms jitter of the recovered clock are 42.37 ps and 7.06 ps for a 5-Gb/s 27-1 PRBS, respectively. Moreover, the measured peak-to-peak jitter and rms jitter of the recovered data are 53.33 ps and 8.89 ps for a 5-Gb/s 27-1 PRBS, respectively.",
author = "Lee, {Yen Long} and Soon-Jyh Chang and Chu, {Rong Sing} and Lin, {Ying Zu} and Chen, {Yen Chi} and Ren, {Goh Jih} and Chung-Ming Huang",
year = "2012",
month = "12",
day = "1",
doi = "10.1109/IPEC.2012.6522645",
language = "English",
pages = "141--144",
note = "2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 ; Conference date: 12-11-2012 Through 14-11-2012",

}

Lee, YL, Chang, S-J, Chu, RS, Lin, YZ, Chen, YC, Ren, GJ & Huang, C-M 2012, 'A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector' 論文發表於 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012, Kobe, Japan, 12-11-12 - 12-11-14, 頁 141-144. https://doi.org/10.1109/IPEC.2012.6522645

A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector. / Lee, Yen Long; Chang, Soon-Jyh; Chu, Rong Sing; Lin, Ying Zu; Chen, Yen Chi; Ren, Goh Jih; Huang, Chung-Ming.

2012. 141-144 論文發表於 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012, Kobe, Japan.

研究成果: Paper

TY - CONF

T1 - A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector

AU - Lee, Yen Long

AU - Chang, Soon-Jyh

AU - Chu, Rong Sing

AU - Lin, Ying Zu

AU - Chen, Yen Chi

AU - Ren, Goh Jih

AU - Huang, Chung-Ming

PY - 2012/12/1

Y1 - 2012/12/1

N2 - This paper presents a 5-Gb/s 1/4-rate clock and data recovery (CDR) circuit. The proposed dynamic stepwise bang-bang phase detector comprises the advantage of linear and bang-bang phase detectors. The CDR adjusts the charge pump currents and the interpolation weight of phase interpolators according to the phase error between input data and feedback clock. This CDR circuit was fabricated in TSMC 1P9M 90-nm CMOS technology. It consumes 16.8 mW from a 1.2-V supply and occupies an active area of 0.3 mm2. The measured peak-to-peak jitter and rms jitter of the recovered clock are 42.37 ps and 7.06 ps for a 5-Gb/s 27-1 PRBS, respectively. Moreover, the measured peak-to-peak jitter and rms jitter of the recovered data are 53.33 ps and 8.89 ps for a 5-Gb/s 27-1 PRBS, respectively.

AB - This paper presents a 5-Gb/s 1/4-rate clock and data recovery (CDR) circuit. The proposed dynamic stepwise bang-bang phase detector comprises the advantage of linear and bang-bang phase detectors. The CDR adjusts the charge pump currents and the interpolation weight of phase interpolators according to the phase error between input data and feedback clock. This CDR circuit was fabricated in TSMC 1P9M 90-nm CMOS technology. It consumes 16.8 mW from a 1.2-V supply and occupies an active area of 0.3 mm2. The measured peak-to-peak jitter and rms jitter of the recovered clock are 42.37 ps and 7.06 ps for a 5-Gb/s 27-1 PRBS, respectively. Moreover, the measured peak-to-peak jitter and rms jitter of the recovered data are 53.33 ps and 8.89 ps for a 5-Gb/s 27-1 PRBS, respectively.

UR - http://www.scopus.com/inward/record.url?scp=84881074272&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84881074272&partnerID=8YFLogxK

U2 - 10.1109/IPEC.2012.6522645

DO - 10.1109/IPEC.2012.6522645

M3 - Paper

AN - SCOPUS:84881074272

SP - 141

EP - 144

ER -

Lee YL, Chang S-J, Chu RS, Lin YZ, Chen YC, Ren GJ 等. A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector. 2012. 論文發表於 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012, Kobe, Japan. https://doi.org/10.1109/IPEC.2012.6522645