This paper presents a 5-Gb/s 1/4-rate clock and data recovery (CDR) circuit. The proposed dynamic stepwise bang-bang phase detector comprises the advantage of linear and bang-bang phase detectors. The CDR adjusts the charge pump currents and the interpolation weight of phase interpolators according to the phase error between input data and feedback clock. This CDR circuit was fabricated in TSMC 1P9M 90-nm CMOS technology. It consumes 16.8 mW from a 1.2-V supply and occupies an active area of 0.3 mm2. The measured peak-to-peak jitter and rms jitter of the recovered clock are 42.37 ps and 7.06 ps for a 5-Gb/s 27-1 PRBS, respectively. Moreover, the measured peak-to-peak jitter and rms jitter of the recovered data are 53.33 ps and 8.89 ps for a 5-Gb/s 27-1 PRBS, respectively.
|出版狀態||Published - 2012|
|事件||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan|
持續時間: 2012 11月 12 → 2012 11月 14
|Other||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012|
|期間||12-11-12 → 12-11-14|
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