A 6-bit 1GS/s low-power flash ADC

Yu Chang Lien, Ying Zu Lin, Soon-Jyh Chang

研究成果: Conference contribution

7 引文 斯高帕斯(Scopus)

摘要

This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13μm CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.

原文English
主出版物標題2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
頁面211-214
頁數4
DOIs
出版狀態Published - 2009 十二月 1
事件2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
持續時間: 2009 四月 282009 四月 30

出版系列

名字2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
國家/地區Taiwan
城市Hsinchu
期間09-04-2809-04-30

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 控制與系統工程
  • 電氣與電子工程

指紋

深入研究「A 6-bit 1GS/s low-power flash ADC」主題。共同形成了獨特的指紋。

引用此