A 6-Bit 2-GS/s flash aanlog-to-digital converter in 0.18-μm CMOS process

Ying Zu Lin, Yen Ting Liu, Soon-Jyh Chang

研究成果: Paper同行評審

4 引文 斯高帕斯(Scopus)

摘要

A 6-bit flash ADC is fabricated in TSMC CMOS 0.18-μm 1P6M process and supports a sampling rate up to 2 GS/s. The proposed ADC consists of a track-and-hold amplifier, a comparator array, a four-channel ROM-based 64-to-6 encoder, a multiplexer, and a clock generation and distribution system. Instead of traditional latch-based comparators used in high-speed ADCs, continuous-time comparators are employed to minimize kick-back noises and offsets. When the sampling frequency is 2 GHz, the measured SNDR is 30.01 dB at input frequency around 200 MHz. The ADC consumes 255 mW from a 1.8-V supply and occupies 1.88 × 1.92 mm2 of die area. In addition to chip implementation, an analysis on resistive averaging network in frequency domain is presented. Characteristics of averaged differential pairs related to input frequency are revealed.

原文English
頁面351-354
頁數4
DOIs
出版狀態Published - 2006 十二月 1
事件2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China
持續時間: 2006 十一月 132006 十一月 15

Other

Other2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
國家/地區China
城市Hangzhou
期間06-11-1306-11-15

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 電子、光磁材料

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