A 6-bit flash ADC is fabricated in TSMC CMOS 0.18-μm 1P6M process and supports a sampling rate up to 2 GS/s. The proposed ADC consists of a track-and-hold amplifier, a comparator array, a four-channel ROM-based 64-to-6 encoder, a multiplexer, and a clock generation and distribution system. Instead of traditional latch-based comparators used in high-speed ADCs, continuous-time comparators are employed to minimize kick-back noises and offsets. When the sampling frequency is 2 GHz, the measured SNDR is 30.01 dB at input frequency around 200 MHz. The ADC consumes 255 mW from a 1.8-V supply and occupies 1.88 × 1.92 mm2 of die area. In addition to chip implementation, an analysis on resistive averaging network in frequency domain is presented. Characteristics of averaged differential pairs related to input frequency are revealed.
|出版狀態||Published - 2006 12月 1|
|事件||2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China|
持續時間: 2006 11月 13 → 2006 11月 15
|Other||2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006|
|期間||06-11-13 → 06-11-15|
All Science Journal Classification (ASJC) codes