A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process

Chun Cheng Liu, Yi Ting Huang, Guan Ying Huang, Soon Jyh Chang, Chung Ming Huang, Chih Haur Huang

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

摘要

This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-μm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.

原文English
主出版物標題2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
頁面215-218
頁數4
DOIs
出版狀態Published - 2009
事件2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
持續時間: 2009 四月 282009 四月 30

出版系列

名字2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
國家/地區Taiwan
城市Hsinchu
期間09-04-2809-04-30

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 控制與系統工程
  • 電氣與電子工程

指紋

深入研究「A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process」主題。共同形成了獨特的指紋。

引用此