A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process

Chun Cheng Liu; Yi Ting Huang; Guan Ying Huang; Soon Jyh Chang; Chung Ming Huang; Chih Haur Huang

doi:10.1109/VDAT.2009.5158133

A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process

Chun Cheng Liu, Yi Ting Huang, Guan Ying Huang, Soon Jyh Chang, Chung Ming Huang, Chih Haur Huang

研究成果: Conference contribution

13 引文斯高帕斯（Scopus）

摘要

This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-μm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm² active area.

原文	English
主出版物標題	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
頁面	215-218
頁數	4
DOIs	https://doi.org/10.1109/VDAT.2009.5158133
出版狀態	Published - 2009
事件	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan 持續時間: 2009 4月 28 → 2009 4月 30

出版系列

名字	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
國家/地區	Taiwan
城市	Hsinchu
期間	09-04-28 → 09-04-30

All Science Journal Classification (ASJC) codes

硬體和架構
控制與系統工程
電氣與電子工程

存取文件

10.1109/VDAT.2009.5158133

其它文件與鏈接

引用此

Liu, C. C., Huang, Y. T., Huang, G. Y., Chang, S. J., Huang, C. M., & Huang, C. H. (2009). A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process. 於 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 (頁 215-218). 文章 5158133 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09). https://doi.org/10.1109/VDAT.2009.5158133

@inproceedings{fe23fa32cae14f4b893c3419a8110442,

title = "A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process",

abstract = "This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-μm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.",

author = "Liu, {Chun Cheng} and Huang, {Yi Ting} and Huang, {Guan Ying} and Chang, {Soon Jyh} and Huang, {Chung Ming} and Huang, {Chih Haur}",

year = "2009",

doi = "10.1109/VDAT.2009.5158133",

language = "English",

isbn = "9781424427826",

series = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

pages = "215--218",

booktitle = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

note = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 ; Conference date: 28-04-2009 Through 30-04-2009",

}

Liu, CC, Huang, YT, Huang, GY, Chang, SJ , Huang, CM & Huang, CH 2009, A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process. 於 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158133, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, 頁 215-218, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, 09-04-28. https://doi.org/10.1109/VDAT.2009.5158133

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T1 - A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process

AU - Liu, Chun Cheng

AU - Huang, Yi Ting

AU - Huang, Guan Ying

AU - Chang, Soon Jyh

AU - Huang, Chung Ming

AU - Huang, Chih Haur

PY - 2009

Y1 - 2009

N2 - This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-μm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.

AB - This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-μm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.

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M3 - Conference contribution

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SN - 9781424427826

T3 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

SP - 215

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BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

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Y2 - 28 April 2009 through 30 April 2009

ER -

A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process

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