This paper presents a 60-GHz high-gain, low-power, 3.7-dB noise-figure (NF), CMOS low-noise amplifier (LNA) fabricated with a 90-nm process. The CMOS LNA exhibited a two-stage cascode structure with a common-source buffer amplifier. To achieve a lower NF and to prevent poor linearity, an inter-stage noise matching inductor and a derivative superposition method were applied to the LNA design. A thin-film microstrip (TFMS) line was used for matching networks and all interconnections. The TFMS line consists of a top metal layer (M9) serving as the signal microstrip line and a bottom metal layer (M1) serving as the ground plane. The measurement results showed that the proposed LNA exhibited the best gain performance of 22 dB at 57.3 GHz and a minimum NF of 3.7 dB at 61 GHz. The input third-order intercept point was -13 dBm. Further, the proposed LNA dissipated a total power of 13.5 mW from a 1.5 V power supply.