摘要
This letter presents the design and implementation of a 60-GHz millimeter-wave RF-integrated-circuit-on-chip bandpass filter using a 0.18-μm standard CMOS process. A planar ring resonator structure with dual-transmission zeros was adopted in the design of this CMOS filter. The die size of the chip is 1.148 × 1.49 mm2. The investigations of sensitivity to the insertion loss and the passband bandwidth for different perturbation stub sizes are also studied. The filter has a 3-dB bandwidth of about 12 GHz at the center frequency of 64 GHz. The measured insertion loss of the passband is about 4.9 dB, and the return loss is better than 10 dB within the passband.
原文 | English |
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頁(從 - 到) | 246-248 |
頁數 | 3 |
期刊 | IEEE Electron Device Letters |
卷 | 29 |
發行號 | 3 |
DOIs | |
出版狀態 | Published - 2008 3月 |
All Science Journal Classification (ASJC) codes
- 電子、光磁材料
- 電氣與電子工程