A 60 GHz millimeter-wave RFIC-on-chip dipole antenna, fabricated with a 0.18μm CMOS process for wireless personal area network, is discussed. A planer dipole-antenna structure with an integrated microstrip via-hole balun is adopted to design this RFIC-on-chip antenna, with a die size of the chip 0.75×0.66 mm. The length of the dipole strips is approximately a /4 wavelength and the ground plane of the microstrip line and the dipole strips are in the same plane. A Finite Element Method based on 3-D full-wave EM solver, HFSS, is also used for design simulation and the simulated antenna radiation pattern is close to an omni-directional pattern. The efficiency of the simulated antenna radiation is 16% due to CMOS substrate loss and the measured maximum antenna power gain is ~10 dB.
|出版狀態||Published - 2007 一月 1|
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