A 65-nm ReRAM-Enabled Nonvolatile Processor with Time-Space Domain Adaption and Self-Write-Termination Achieving $> 4× Faster Clock Frequency and $> 6× Higher Restore Speed

Zhibo Wang, Yongpan Liu, Albert Lee, Fang Su, Chieh Pu Lo, Zhe Yuan, Jinyang Li, Chien Chen Lin, Wei Hao Chen, Hsiao Yun Chiu, Wei En Lin, Ya Chin King, Chrong Jung Lin, Pedram Khalili Amiri, Kang Lung Wang, Meng Fan Chang, Huazhong Yang

研究成果: Article同行評審

6 引文 斯高帕斯(Scopus)

摘要

With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well as 'normally off' applications. Recently, zero-standby power and fast switching nonvolatile processors (NVPs) have been proposed based on emerging nonvolatile memories (NVMs), such as ferroelectric RAM or spin-transfer-torque magnetic RAM. However, previous NVPs store all data to NVM upon every power interruption, resulting in high-energy consumption and degraded NVM endurance. This paper presents a 65-nm fully CMOS-logic-compatible ReRAM-based NVP supporting time-space domain adaption. It incorporates adaptive nonvolatile controller, nonvolatile flip-flops, and nonvolatile static random access memory (nvSRAM) with self-write termination. Data redundancy in both time and space domain is fully exploited to reduce store/restore time/energy and boost clock frequency. The NVP operates at >100 MHz and achieves 20 ns/0.45 nJ restore time/energy, realizing >6 × and >6000 × higher speed and energy efficiency of restore and >4 × faster operating frequency compared with that of state of the art.

原文English
文章編號8003272
頁(從 - 到)2769-2785
頁數17
期刊IEEE Journal of Solid-State Circuits
52
發行號10
DOIs
出版狀態Published - 2017 十月

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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