TY - GEN
T1 - A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic
AU - Liu, Yongpan
AU - Wang, Zhibo
AU - Lee, Albert
AU - Su, Fang
AU - Lo, Chieh Pu
AU - Yuan, Zhe
AU - Lin, Chien Chen
AU - Wei, Qi
AU - Wang, Yu
AU - King, Ya Chin
AU - Lin, Chrong Jung
AU - Khalili, Pedram
AU - Wang, Kang Lung
AU - Chang, Meng Fan
AU - Yang, Huazhong
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/2/23
Y1 - 2016/2/23
N2 - With the rising importance of energy efficiency, zero leakage power and instant-on capability are highly desired features in energy harvesting sensors, as well as normally off high performance processors. However, intermittent power in such systems requires nonvolatile memory (NVM) to hold intermediate data and avoid rollbacks. Previous work has adopted FeRAM and STT-MRAM to achieve zero-standby power and fast-restore nonvolatile processors (NVPs) [1-3]. Previous NVPs, however, suffer from several drawbacks: 1) Various power interrupt periods are not considered; 2) the 2-macro memory architecture slows access speed; 3) worst-case store/restore operations are always performed. We present a 65nm fully-CMOS-logic-compatible ReRAM-based NVP achieving time/space-adaptive data retention. A 1-macro nvSRAM with self-write-termination (SWT) is integrated to boost clock frequency and reduce store energy. The adaptive retention and SWT strategy relieve the ReRAM write endurance challenge (106-1012), making it sufficient for most applications. The NVP operates at 100MHz with 20ns/0.45nJ restore time (TRESTORE)/energy (ERESTORE), realizing 6× reduction in TRESTORE, >6000× reduction in ERESTORE and 4× higher clock frequency compared with existing designs.
AB - With the rising importance of energy efficiency, zero leakage power and instant-on capability are highly desired features in energy harvesting sensors, as well as normally off high performance processors. However, intermittent power in such systems requires nonvolatile memory (NVM) to hold intermediate data and avoid rollbacks. Previous work has adopted FeRAM and STT-MRAM to achieve zero-standby power and fast-restore nonvolatile processors (NVPs) [1-3]. Previous NVPs, however, suffer from several drawbacks: 1) Various power interrupt periods are not considered; 2) the 2-macro memory architecture slows access speed; 3) worst-case store/restore operations are always performed. We present a 65nm fully-CMOS-logic-compatible ReRAM-based NVP achieving time/space-adaptive data retention. A 1-macro nvSRAM with self-write-termination (SWT) is integrated to boost clock frequency and reduce store energy. The adaptive retention and SWT strategy relieve the ReRAM write endurance challenge (106-1012), making it sufficient for most applications. The NVP operates at 100MHz with 20ns/0.45nJ restore time (TRESTORE)/energy (ERESTORE), realizing 6× reduction in TRESTORE, >6000× reduction in ERESTORE and 4× higher clock frequency compared with existing designs.
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U2 - 10.1109/ISSCC.2016.7417918
DO - 10.1109/ISSCC.2016.7417918
M3 - Conference contribution
AN - SCOPUS:84962909942
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 84
EP - 86
BT - 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
Y2 - 31 January 2016 through 4 February 2016
ER -