A 7 Gb/s half-rate clock and data recovery circuit with compact control loop

Yu Po Cheng, Yen Long Lee, Ming Hung Chien, Soon-Jyh Chang

研究成果: Conference contribution

摘要

This paper presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency for digital-based clock and data recovery circuits (CDRs). By combining the frequency control loop and integral path with a digital adder, some tributary circuits are removed to save total area and power. Meanwhile, the stepwise control technique for constant system bandwidth is digitalized to enhance the system robustness. The digital-based CDR is designed and fabricated in 90-nm GUTM CMOS process. The measured root mean square (rms) jitter ratio of the synchronous clock and recovered data are 3.2% (9.25 ps) and 0.048UI (13.66 ps) and the peak to peak jitter are 64.38 ps (22.5 %) and 65.63 ps (23 %) while the input data pattern is 7 Gb/s PRBS7. The core area of the test chip is 0.054 mm2 and its power efficiency is 1.623 mW/Gb/s.

原文English
主出版物標題2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467394987
DOIs
出版狀態Published - 2016 五月 31
事件2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
持續時間: 2016 四月 252016 四月 27

出版系列

名字2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
國家Taiwan
城市Hsinchu
期間16-04-2516-04-27

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation

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