摘要
This paper proposes averaging correlated level shifting (ACLS) and reference swapping (RS) techniques for simultaneously reducing errors from the finite opamp gain and capacitor mismatch in a pipelined analog-to-digital converter (ADC). The ACLS technique reduces the sensitivity of ADC accuracy to the opamp gain by averaging the finite opamp gain errors in two amplifying phases, where the error in the second amplifying phase is designed to have the opposite polarity to the one in the first amplifying phase. Meanwhile, ACLS also decreases the opamp's thermal noise. In addition, the RS utilizes the averaging operation to reduce capacitor random mismatch error and combines a simple capacitor layout arrangement to decrease capacitor gradient mismatch error. Using the ACLS and RS techniques, a 16-bit ring amplifier-based pipelined ADC without calibration is realized in a 90-nm CMOS technology. Operating at 24 MS/s for a 10-MHz sine wave input, the proposed ADC achieves a 74.3-dB signal-to-noise-and-distortion ratio (SNDR) and 85.5-dB spurious free dynamic range (SFDR), and consumes 5.1 mW, yielding Walden and Schreier figure of merits of 50.1 fJ/conversion-step and 168 dB, respectively.
| 原文 | English |
|---|---|
| 文章編號 | 08645697 |
| 頁（從 - 到） | 1425-1435 |
| 頁數 | 11 |
| 期刊 | IEEE Journal of Solid-State Circuits |
| 卷 | 54 |
| 發行號 | 5 |
| DOIs | |
| 出版狀態 | Published - 2019 五月 1 |
指紋
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
引用此文
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A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch. / Hung, Tsung Chih; Kuo, Tai-Haur.
於: IEEE Journal of Solid-State Circuits, 卷 54, 編號 5, 08645697, 01.05.2019, p. 1425-1435.研究成果: Article
TY - JOUR
T1 - A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch
AU - Hung, Tsung Chih
AU - Kuo, Tai-Haur
PY - 2019/5/1
Y1 - 2019/5/1
N2 - This paper proposes averaging correlated level shifting (ACLS) and reference swapping (RS) techniques for simultaneously reducing errors from the finite opamp gain and capacitor mismatch in a pipelined analog-to-digital converter (ADC). The ACLS technique reduces the sensitivity of ADC accuracy to the opamp gain by averaging the finite opamp gain errors in two amplifying phases, where the error in the second amplifying phase is designed to have the opposite polarity to the one in the first amplifying phase. Meanwhile, ACLS also decreases the opamp's thermal noise. In addition, the RS utilizes the averaging operation to reduce capacitor random mismatch error and combines a simple capacitor layout arrangement to decrease capacitor gradient mismatch error. Using the ACLS and RS techniques, a 16-bit ring amplifier-based pipelined ADC without calibration is realized in a 90-nm CMOS technology. Operating at 24 MS/s for a 10-MHz sine wave input, the proposed ADC achieves a 74.3-dB signal-to-noise-and-distortion ratio (SNDR) and 85.5-dB spurious free dynamic range (SFDR), and consumes 5.1 mW, yielding Walden and Schreier figure of merits of 50.1 fJ/conversion-step and 168 dB, respectively.
AB - This paper proposes averaging correlated level shifting (ACLS) and reference swapping (RS) techniques for simultaneously reducing errors from the finite opamp gain and capacitor mismatch in a pipelined analog-to-digital converter (ADC). The ACLS technique reduces the sensitivity of ADC accuracy to the opamp gain by averaging the finite opamp gain errors in two amplifying phases, where the error in the second amplifying phase is designed to have the opposite polarity to the one in the first amplifying phase. Meanwhile, ACLS also decreases the opamp's thermal noise. In addition, the RS utilizes the averaging operation to reduce capacitor random mismatch error and combines a simple capacitor layout arrangement to decrease capacitor gradient mismatch error. Using the ACLS and RS techniques, a 16-bit ring amplifier-based pipelined ADC without calibration is realized in a 90-nm CMOS technology. Operating at 24 MS/s for a 10-MHz sine wave input, the proposed ADC achieves a 74.3-dB signal-to-noise-and-distortion ratio (SNDR) and 85.5-dB spurious free dynamic range (SFDR), and consumes 5.1 mW, yielding Walden and Schreier figure of merits of 50.1 fJ/conversion-step and 168 dB, respectively.
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U2 - 10.1109/JSSC.2019.2891650
DO - 10.1109/JSSC.2019.2891650
M3 - Article
AN - SCOPUS:85065102470
VL - 54
SP - 1425
EP - 1435
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 5
M1 - 08645697
ER -