A 7b 4.5GS/s 4× Interleaved SAR ADC with Fully On-Chip Background Timing Skew Calibration

With the development of broadband wireless communication and DSP-based wireline communication, there is a rising demand for medium-resolution (68bit) ADCs with multi-gigahertz sampling rates and low power consumption. Thus, the time-interleaved SAR ADC is a great choice with high energy efficiency and robust sub-channels. However, costly calibration engines are usually required to resolve channel mismatches, especially timing skew mismatch related to the input signal. Digital detection methods are often limited by the type of input signal, require a long time to converge, and consume area and power. A few analog techniques employ a timing reference signal to simplify the detection mechanisms [1], [2]. However, prior art [1] puts the timing reference signal in the same path as the input signal, which complicates its timing and increases subchannel conversion time. In [2] a modulated reference clock injection path on the CDAC is added and obtains the timing skew from the digitized injected voltage. Even though the extra conversion time is saved, digital circuits for demodulation are required, and the skew-related voltage on the CDAC is so small that digital units require 1M average cycles to improve accuracy. This work presents a background timing skew calibration that achieves input independence by common-mode voltage injection. Furthermore, a replica switch in the sampler is added to isolate the calibration circuit from the quantizer. This simplifies the detection circuit and makes it shared among the four channels to reduce errors. With a near 4GHz input, the presented technique suppresses the timing skew tones below -52dB in <12K samples.