A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

Ying Zu Lin, Chun Cheng Liu, Guan Ying Huang, Ya Ting Shyu, Soon-Jyh Chang

研究成果: Conference contribution

41 引文 斯高帕斯(Scopus)

摘要

This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversionstep, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.

原文English
主出版物標題2010 Symposium on VLSI Circuits, VLSIC 2010
頁面243-244
頁數2
DOIs
出版狀態Published - 2010 十月 22
事件2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States
持續時間: 2010 六月 162010 六月 18

出版系列

名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2010 24th Symposium on VLSI Circuits, VLSIC 2010
國家United States
城市Honolulu, HI
期間10-06-1610-06-18

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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