A 9-bit 150-MS/s subrange ADC based on SAR architecture in 90-nm CMOS

Ying Zu Lin, Chun Cheng Liu, Guan Ying Huang, Ya Ting Shyu, Yen Ting Liu, Soon Jyh Chang

研究成果: Article同行評審

57 引文 斯高帕斯(Scopus)

摘要

This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation- register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively.

原文English
文章編號6459552
頁(從 - 到)570-581
頁數12
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
60
發行號3
DOIs
出版狀態Published - 2013 二月 15

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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