A 9-bit 50 MS/s CBSC pipelined ADC using time-shifted correlated double sampling

Po Chun Hsiao, I. Jen Chao, Chung Lun Hsu, Bin Da Liu, Chun Yueh Huang, Soon Jyh Chang

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

Comparator-based switched-capacitor (CBSC) circuit provides a solution for insufficient impedance of the transistor in the advanced process, but the accuracy suffers from the overshoot error caused by comparator delay. In this paper, a time-shifted correlated double sampling (TSCDS) scheme for CBSC circuit is proposed to alleviate the overshoot error as well as mitigating double loading. Moreover, we propose an overshoot correction technique to further suppress the overshoot after employing TSCDS. Speed bottleneck in the conventional CBSC circuit is limited by the fine discharging phase. With the proposed TSCDS and the overshoot correction, the CBSC circuit exploits the coarse charging and removes the fine discharging phase to achieve a 9-bit 50 MS/s pipelined ADC. Simulation results demonstrate a 54.3-dB SNDR is achieved with 3.65-mW power consumption in 90-nm CMOS process and 1.2-V supply.

原文English
主出版物標題54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
出版狀態Published - 2011 十月 13
事件54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
持續時間: 2011 八月 72011 八月 10

出版系列

名字Midwest Symposium on Circuits and Systems
ISSN(列印)1548-3746

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
國家Korea, Republic of
城市Seoul
期間11-08-0711-08-10

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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