A 9.8-fJ/conv.-step FoMW8b 2.5-GS/s Single-Channel CDAC-Assisted Subranging ADC with Reference-Embedded Comparators

Jia Ching Wang, Bing Yang Li, Tai Haur Kuo

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

This paper presents an 8b 2.5-GS/s single-channel CDAC-assisted three-stage subranging ADC using reference-embedded comparators (RECs). In this work, both the power consumption and calibration overhead of the RECs are largely reduced by a simple capacitor DAC (CDAC) designed for this subranging ADC. In addition, the severe CDAC gain error is also largely reduced by a simple gain error compensation design, which is not only insensitive to the PVT variation but is also a low-complexity design. This ADC is implemented in 28-nm CMOS technology and occupies an active area of 0.024 mm2. With a Nyquist-rate input at 2.5 GS/s, the measured SNDR is 44.8 dB with a 3.5-mW power consumption only. This ADC achieves a Walden Figure-of-Merits of 9.8 fJ/conv.-step only. Compared to the single-channel prior-art ADCs with a sampling rate =1.5 GS/s and a resolution of 6-10b, this work advances the state-of-the-art by nearly 2×.

原文English
主出版物標題2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
發行者Institute of Electrical and Electronics Engineers Inc.
頁面92-93
頁數2
ISBN(電子)9781665497725
DOIs
出版狀態Published - 2022
事件2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States
持續時間: 2022 6月 122022 6月 17

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2022-June
ISSN(列印)0743-1562

Conference

Conference2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
國家/地區United States
城市Honolulu
期間22-06-1222-06-17

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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